Synopsys, Inc.

Joydeep Banerjee

Debabrata Das Roy

Solaiman Rahim

Mayur Bubna

A method includes: receiving a simulation vector associated with a circuit design, wherein the simulation vector is associated with a simulation vector type; identifying, by a processor, a plurality of glitch transitions from among one or more transitions associated with a pin of a cell of the circuit design during a clock period of the simulation vector, and determining a glitch power consumption of the cell during the clock period based on the plurality of glitch transitions.

Glitch identification and power analysis using simulation vectors

A method includes acquiring a vector data signal associated with a circuit design, performing a timing update to determine timing information for the circuit design, and identifying a glitch in the circuit design based on a shifted vector waveform. The timing information includes a signal delay associated with a cell of the circuit design. The shifted vector waveform is generated by shifting the vector data signal based on the timing information.

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Karnataka, India

Joydeep Banerjee