International Business Machines Corporation

Joyce E Acocella

Louis L Hsu

Seiki Ogura

Joseph F Shepard

Nivo Rovedo

Carol Galli

Randy William Mann

A nonvolatile memory cell utilizing planar control gates, which provides advantages of being compatible with self-aligned silicide processes and providing a planar surface for subsequent wiring processes. A substrate defines a first NVRAM region having large floating gate areas with smaller areas cutout to isolate individual memory cells, and a second CMOS Logic region. ONO is deposited on the floating gate areas, and a thick poly layer is deposited in a blanket manner over the first and second regions of the substrate. Resist shapes are patterned over the logic areas in the array where necessary according to a predetermined density algorithm. The poly layer is reactive ion etched, followed by a chemical mechanical polishing (CMP) operation. The final poly gate thickness is 200-220 nm in the CMOS logic areas and in the NVRAM control gate areas between floating gate regions, but only 100-120 nm for the NVRAM control gates over the floating gates. The control gate physical thickness is decoupled (isolated) from the standard logic by standard photoetching processes, and the final structure appears identical from a topological perspective to a standard CMOS structure.

Method of making NVRAM cell with planar control gate

Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

Packing density for flash memories

Packing density for flash memories by using a pad oxide

A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain form a self-aligned aperture for a surface strap that insulates the strap from misaligned portions of the gate stack.

DRAM cell having raised source, drain and isolation

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Hopewell Junction, NY, United States of America

Joyce E Acocella