Adeia Semiconductor Bonding Technologies Inc.

Joy Watanabe

Belgacem Haba

Cyprian Emeka Uzoh

Rajesh Katkar

Guilian Gao

Gaius Gillman Fountain, Jr

Laura Wills Mirkarimi

Gabriel Z Guevara

Thomas Workman

Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Direct bonded stack structures for increased reliability and improved yield in microelectronics

Growing community of inventors

Campbell, CA, United States of America

Joy Watanabe