Synopsys, Inc.

Jovanka Ciric Vujkovic

Kenneth S McElvain

Janet L Olson

Eyal Odiz

Van E Morgan

Deepak Dattatraya Sherlekar

Patrick Vuillod

Jiong Luo

Luca Gaetano Amaru

Mohammad Ziaullah Khan

Jeff Ku

Linuo Xue

Guilherme Augusto Flach

Mayank Jain

Peter Moceyunas

Casey The

A system receives a logic design of a circuit of an integrated circuit and apply a reduced synthesis process to the logical design of the integrated circuit. The reduced synthesis process is less computation intensive compared to the optimized digital implementation synthesis process and generates a netlist having suboptimal delay. The system provides the generated netlist as input to a timing analysis that alters the standard delay computation (through scaling and other means) to predict the timing of a fully optimized netlist. The reduced synthesis process has faster execution time compared to the optimized digital implementation synthesis process but results in comparable performance, power and area that is within a threshold of the results generated using optimized digital implementation synthesis process.

Fast synthesis of logical circuit design with predictive timing

Embodiments herein describe a techniques for identifying a first combinational cellin a design for an integrated circuit, identifying a plurality of candidate combinational cellsto combine with the first combinational cell using a first criterion. The techniques also include combining the first combinational cell with at least one of the plurality of candidate combinational cells to form a multi-bit (MB) combinational cell. Upon determining the MB combinational cell satisfies a performance threshold, the first combinational cell and the at least one of the plurality of candidate combinational cells are replaced with the MB combinational cell in the design.

Integrated circuit design using multi-bit combinational cells

Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiment can perform enumeration on a hardware description language (HDL) description of an IC design to obtain a enumerated IC design that includes at least one technology-independent wide-gate or technology-independent wide-bus, wherein the technology-independent wide-gate represents a logical function that is performed on a variable number of inputs, and wherein the technology-independent wide-bus represents a variable number of signals that are part of a bus. The embodiments can then perform technology-independent IC optimization, synthesis, and technology-dependent IC optimization to obtain an optimized and synthesized IC design.

Optimizing an integrated circuit (IC) design comprising at least one wide-gate or wide-bus

Methods and systems for optimizing and/or designing integrated circuits. In one embodiment, a method for dynamically routing a net from equivalent resources is described, comprising identifying a critical load, determining whether a driver driving the critical load drives other components, and whether the critical load requires an improvement in slack, replicating the driver, to create a replicated driver, when the critical load requires an improvement in slack, coupling the replicated driver to the load; and tagging the replicated driver.

Optimizing designs of integrated circuits

Systems and techniques are described for designing an integrated circuit (IC). Some embodiments identify and preserve slices by using new objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such slice objects. These new objects can enable rapid access and preservation of slices, thereby improving the runtime and/or quality of results (QoR) of an IC design system.

Identifying and using slices in an integrated circuit (IC) design

Systems and techniques are described for designing an integrated circuit (IC). Some embodiments explicitly represent wide-buses as distinct objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such wide-bus objects. These new objects can enable rapid access and preservation of wide-buses, thereby improving the runtime and/or quality of results (QoR) of an IC design system.

Creating and using a wide-bus data structure to represent a wide-bus in an integrated circuit (IC) design

Systems and techniques are described for designing an integrated circuit (IC). Some embodiments explicitly represent wide-gates as distinct objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such wide-gate objects. These new objects can enable rapid access and preservation of wide-gates, thereby improving the runtime and/or quality of results (QoR) of an IC design system.

Creating and using a wide-gate data structure to represent a wide-gate in an integrated circuit (IC) design

Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes determining fanout of a driving component in a representation of an integrated circuit (IC) being designed, determining for the driving component, the loads in the representation of the IC driven by the driving component, and determining use of existing wiring resources used to connect the loads to the driving component. The method further includes optimizing, based on the use of existing wiring resources, the fanout of the driving component, and the loads being driven by the driving component, a design of the IC.

Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes routing, as part of a process of designing an integrated circuit (IC), connections on a representation of the IC using a first set of wiring resources and marking wiring resources as used once the wiring resources within the first set have been used for routing and routing, using a second set of wiring resources in the representation, connections on the IC without checking whether wiring resources within the second set have been previously used to route connections, wherein wiring resources in the second set differ, on average, in physical size, from wiring resources in the first set. Other methods and systems for optimizing and/or designing ICs are also described, and machine-readable media containing executable program instructions which cause systems to perform one or more of these methods are also described.

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Mountain View, CA, United States of America

Jovanka Ciric Vujkovic