Yonsei University

Jounghoo Lee

Youngsok Kim

Suhyun Lee

Jaeyong Song

Jinho Lee

Yeonan Ha

Mingi Yoo

An apparatus for accelerating neural networks, includes: a memory for storing graph input data including vertices and edges; an aggregation engine that processes the accumulation of features and generates feature vectors by taking the graph input data and performing an aggregation operation on the graph input data; an on-chip cache for caching the feature vectors; and a combination engine that generates a systolic array for matrix multiplications based on the feature vectors taken from the on-chip cache and weights taken from the memory.

Apparatus for accelerating neural networks

There is provided a graphics processor performance analysis apparatus. The apparatus includes a model definition unit that defines a graphics processor core model for identifying structural stalls of computing and a memory, a data stall of the memory, and an idle stall, a simulation execution unit that simulates an operation of a specific GPU by using architecture parameters of a GPU application and the specific GPU as inputs on the basis of the graphics processor core model, and a performance analysis unit that receives an output of the graphics processor core model as a result of the simulation and analyzes performance of the specific GPU.

Apparatus and method for analyzing graphics processor performance based on graphics processor analytical model

Growing community of inventors

Seoul, South Korea

Jounghoo Lee