Skhynix Inc.

Joung Young Lee

Dong Sop Lee

Yeong Sik Yi

Dae Geun Jee

Dong Jae Shin

Duk Rae Lee

The present technology includes a controller and a memory system including the same. The controller includes a descriptor manager configured to generate descriptors including logical addresses and physical addresses respectively mapped to the logical addresses, a map cache configured to store the descriptors in a linear structure and a binary tree structure, and a map search engine configured to search for a descriptor corresponding to a logical address received from an external device among the descriptors stored in the map cache by performing a linear search method, a binary search method, or both, according to a status of the map cache.

Controller including map cache and memory system including controller

There are provided a controller, an electronic system including the same, and an operating method of the controller and the memory system. The controller includes: a randomizing circuit configured to generate random data having a set number of bits; a masking circuit configured to output select random data by extracting some data according to a number of bits on which a partial encoding operation is to be performed, among the random data; an operating circuit configured to output encoded data and a portion of original data, by performing an operation sequentially on the original data and the select random data; and a cyclic redundancy check circuit configured to generate a cyclic redundancy check value by performing a cyclic redundancy check on the encoded data and the portion of original data, and output partially encoded data including the cyclic redundancy check value, the portion of original data, and the encoded data.

Controller and operating method thereof

Provided herein may be a memory controller configured to control a memory device. The memory controller may include a map buffer, a descriptor queue, and a descriptor controller. The map buffer may sequentially store map segments of a plurality of map segments stored in the memory device. The descriptor queue may store descriptors corresponding to the respective map segments, based on a plurality of addresses of the map buffer. The descriptor controller may search for a target descriptor among the stored descriptors based on a logical address received from a host, and reorder the stored descriptors while searching for the target descriptor.

Reordering a descriptor queue while searching the queue of descriptors corresponding to map segments

An address search circuit of a semiconductor memory apparatus may include a first search interface configured to receive a search command, generate a first signal when a reference count of the target logical address is less than a threshold value, and generate a second signal when the reference count of the target logical address is equal to or more than the threshold value, a second search interface configured to receive map data whose respective reference counts are less than the threshold value in response to the first signal, a search memory configured to store map data whose respective reference counts are equal to or more than the threshold value, a first search buffer configured to store the map data received through the second search interface, and receive map data in response to the second signal; and a search engine configured to select map data by searching the map data.

Address search circuit and method of semiconductor memory apparatus and controller therefor

A controller is coupled to a non-volatile memory device and a host. The controller is configured to perform a cyclic redundancy check on map data associated with user data stored in the memory device, generate an encryption code based on a logical address included in the map data, generate encrypted data through a logical operation on the encryption code and the map data, and transmit the encrypted data to the host.

Apparatus and method for sharing data in a data processing system

A data storage device may include a storage; and a controller, wherein the controller comprises: an address translator configured to generate multiple map data, each including a physical address of the storage corresponding to a logical address and multiple meta data for the multiple map data respectively; a descriptor cache manager configured to add new meta data to a storage area of a descriptor cache, the storage area for the new meta data being physically continuous with a storage area in which last meta data, of the multiple meta data, is stored and assign a head pointer and a tail pointer to select positions in the descriptor cache; a map cache manager configured to store the multiple map data in a map cache; and a map search component configured to search the descriptor cache according to a search range determined by the head pointer and the tail pointer.

Data storage device, operation method thereof, and storage system including the same

Embodiments of the present disclosure relate to a memory system, a memory controller and an operating method, which allocate one or more of a plurality of buffer slots in a buffer pool to a write buffer as write buffer slots or to a read buffer as read buffer slots, configures initial values of count information on the respective write buffer slots and the respective read buffer slots, which indicate remaining allocation periods respectively, and updates the count information on each of at least some of the write buffer slots when data is written to the write buffer or updates the count information on each of at least some of the read buffer slots when data is read out from the read buffer, thereby providing optimal data read and write performance and minimizing overhead caused in the process of dynamically changing the buffer size.

Memory system, memory controller, and operation method

A controller and a memory system including the same are disclosed. The controller receives a write command for storing write data, which is stored in at least one among a plurality of memory regions included in a host memory, in a nonvolatile memory device, generates a host memory map table by mapping virtual addresses to host memory physical addresses corresponding to the at least one memory region, and transmits the write data stored in the at least one memory region to the nonvolatile memory device by converting the virtual addresses into the host memory physical addresses based on the host memory map table.

Controller and memory system including the same

A controller, an operating method thereof, and a memory system including the same are disclosed. The controller includes a controller for controlling a nonvolatile memory device according to a request from a host with a host memory. The controller includes an address unit configured to divide regions of the host memory, which is allocated as a host memory buffer (HMB), to generate a plurality of sub HMB regions, determine index values of the plurality of sub HMB regions, and generate an HMB map table by mapping virtual addresses to the index values; and a memory control module configured to access at least one among the plurality of sub HMB regions based on the HMB map table. The virtual addresses may be set to continuous values with respect to the plurality of sub HMB regions.

Controller, operating method thereof, and memory system including the same

There are provided a memory system and an operating method thereof. A memory system includes: a nonvolatile memory device that operates in response to a plurality of internal commands received thereby; and a memory controller for generating and queuing the plurality of internal commands in response to a plurality of commands received from a host, and generating and storing a processing completion bitmap index corresponding to the plurality of queued internal commands.

Memory system and operating method thereof

There are provided a memory system and an operating method thereof. A memory system includes: a semiconductor memory device for including a plurality of semiconductor memories, and operating in response to a plurality of internal commands received thereto; and a controller for generating and queuing the plurality of internal commands in response to a plurality of commands received from a host, and generating and storing a master bitmap including information on unperformed operations that are not performed in the semiconductor memory device for internal commands among the plurality of queued internal commands. The controller generates a flush bitmap corresponding to a flush command, using a current master bitmap, when the flush command is received from the host, and clears the flush bitmap if the semiconductor memory device completes the unperformed operations.

A semiconductor device may include a first processor transferring a plurality of command data sets, a mailbox receiving and storing the plurality of command data sets, and a second processor receiving command data sets of the mailbox, wherein the first processor may transfer at least one abort slot number to the mailbox, and wherein the mailbox may search and abort a command data set having a slot number which is identical to an abort slot number among the plurality of command data sets.

Growing community of inventors

Gyeonggi-do, South Korea

Joung Young Lee