Samsung Electronics Co., Ltd.

Joung-Yeal Kim

Sung-Hoon Kim

Seong-Jin Jang

Kyoung-Ho Kim

Young-Hyun Jun

Bai-Sun Kong

Jin-seok Kwak

Jung-bae Lee

Reum Oh

Young-chul Cho

Sang-Yun Kim

Chul-woo Yi

Tai-Young Ko

Sang-kyun Park

Sam-Young Bang

Jong-Hyun Choi

Kwang-il Park

Ho-Young Song

Woo-Jin Lee

Su-Jin Park

Jeong-Don Lim

Se-Il Oh

Dae-Hyun Kwon

Jung-Yong Lee

Seok-jae Lee

Yong-Gwon Jeong

Mi-Young Woo

Chang-Man Khang

Joon-Sun Yoon

Ju-Suk Bang

Chae-Il Lim

A memory controller transmits one or more command pairs of a self-refresh entry command and a subsequent self-refresh exit command to a semiconductor memory device during a refresh period. The semiconductor memory device includes a memory cell array including a plurality of memory cell rows each including a plurality of dynamic memory cells, and a refresh control circuit. The refresh control circuit performs a refresh operation on all of the memory cell rows during the refresh period in a self-refresh mode, the self-refresh mode of the refresh period being configured in response to each self-refresh entry command of the one or more command pairs, for each of the one or more command pairs, the memory controller sequentially transmits during the refresh period at least one self-refresh entry command and at least one self-refresh exit command to the semiconductor memory device separated by one or more time gaps.

Semiconductor memory devices, memory systems and refresh methods of the same

A semiconductor device may include a first terminal electrically connected to a first semiconductor chip, a second terminal electrically connected to a second semiconductor chip, which is different from the first semiconductor chip, a first signal line electrically connecting the first terminal and the second terminal and including a first node, a third terminal connected to a tester monitoring a signal transmitted between the first semiconductor chip and the second semiconductor chip, a fourth terminal applied a reference voltage, a second signal line electrically connecting the third terminal and the fourth terminal and including a second node, a first resistor connected between the first node and the second node and a second resistor directly connected to the second node different from the first resistor.

Semiconductor device and semiconductor package comprising the same

A semiconductor device includes: a second transistor having a second conductive type formed on a first well region having a first conductive type; a first transistor having a first conductive type formed on a second well region having a second conductive type; a first well guard ring having the first conductive type, the first well guard ring including at least a first portion formed between the first transistor and the second transistor; a second well guard ring having the first conductive type, the second well guard ring including at least a first portion formed between the first transistor and the second transistor; and a first capacitor formed on at least one of the first well region and the second well region, and located between the first portion of the first well guard ring and the first portion of the second well guard ring.

Semiconductor device and semiconductor memory device including capacitor

A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

Memory device from which dummy edge memory block is removed

A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.

Bitline sense amplifier, memory core including the same and method of sensing charge from a memory cell

A semiconductor device pad is configured to have the same voltage level as that of a semiconductor substrate. The pad includes a semiconductor substrate having a junction area doped with a high concentration of impurity ions, a polylayer portion at least a portion of which is electrically connected to the junction area and a metal layer portion electrically connected to the polylayer portion and receiving a voltage externally applied. The metal layer is configured to transfer the received voltage to the semiconductor substrate.

Semiconductor device pad having the same voltage level as that of a semiconductor substrate

A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.

CMOS charge pump with improved latch-up immunity

Provided is a semiconductor device for performing charge pumping. The semiconductor device may include a first pumping unit, a second pumping unit, and a controller. The first pumping unit may be configured to output a boosted voltage via an output node by using a first input signal and the initial voltage, where the boosted voltage is greater than an initial voltage. The second pumping unit may be configured to output the boosted voltage via the output node by using a second input signal and the initial voltage. The controller may be configured to control the first and second pumping units. Each of the first and second pumping units may include an initialization unit, a boosting unit, and a transmission unit. The initialization unit may be configured to control a voltage of a boosting node to be equal to the initial voltage during an initialization operation. The boosting unit may be configured to boost the voltage of the boosting node based on the first and second input signals. Also, the transmission unit may be configured to control output of the boosted voltage.

Semiconductor device for charge pumping

A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

Latency control circuit and method thereof and an auto-precharge control circuit and method thereof

A structure for controlling the size of a transistor may include: an active region; a first gate line on the active region; one or more second gate lines on the active region; and source or drain regions arranged in three or more divided active regions that result from the first gate line and the one or more second gate lines dividing the active region into the divided active regions. A method of controlling the size of a transistor may include: arranging an active region; arranging a first gate line on the active region; arranging one or more second gate lines on the active region; arranging source or drain regions in three or more divided active regions; and controlling the size of the transistor by connecting to each other or separating from each other the source or drain regions using upper wires.

Transistor layout structures for controlling sizes of transistors without changing active regions, and methods of controlling the same

A charge pump circuit includes initialization units, each of which initializes a boost node to an initialization voltage. Boosting units each boost the boost node to a higher voltage than the initialization voltage in response to an input voltage. First and second pump circuits each include a transfer unit for transferring a voltage of the boost node to an output node and sharing the output node. The transfer unit of the first pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the first pump circuit and the voltage of the boost node of the second pump circuit. The transfer unit of the second pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the second pump circuit and the voltage of the boost node of the first pump circuit.

Charge pump circuit

According to an example embodiment, a semiconductor memory device may include a memory core, input circuit, and/or an output circuit. The input circuit may be configured to generate second data from first data using latch circuits operating in response to input control signals enabled during different periods. The input circuit may be further configured to provide the second data to the memory core. The second data may have 2N times the number of bits of the first data, where N is a positive integer. The output circuit may be configured to generate fourth data from third data using latch circuits operating in response to output control signals enabled during different periods. The output circuit may be further configured to provide the fourth data to data output pins. The fourth data may have &#xbd;N times the number of bits of the third data. A method of inputting/outputting data is also provided.

Semiconductor memory device and method of inputting/outputting data

An address buffer circuit for a semiconductor memory device wherein an address buffer is enabled (to output an internal address signal) in response to a first level of a control signal and, but is disabled in response to a second level of the control signal. An address buffer control unit generates the control signal at the second level in 'no operation' state (NOP command) in which the semiconductor memory device does not perform data accessing operations and generates the control signal at the first level while the semiconductor memory device performs data accessing operations, thereby reducing or minimizing the output of an internal address buffered and output by the address buffer at and thus reducing power consumption during no-operation states of the semiconductor memory device.

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Yongin-si, South Korea

Joung-Yeal Kim