Applied Materials, Inc.

Joung Joo Lee

Xianmin Tang

Fuhong Zhang

Bencherki Mebarki

Seshadri Ganguli

Keith A Miller

Adolph Miller Allen

Annamalai Lakshmanan

Feihu Wang

Srinivas Gandikota

Yixiong Yang

Suketu Arun Parikh

Jacqueline S Wrench

Xiangjin Xie

Rong Tao

Shirish A Pethe

Alexander Jansen

Shouyin Zhang

Feng Quan Liu

Rongjun Wang

Roey Shaviv

Martin Lee Riker

Xiaodong Wang

William Fruchterman

Mei Yin Chang

Avgerinos V Gelatos

Tza-Jing Gung

Jianshe Tang

Zhebo Chen

Huixiong Dai

Kai Wu

Tae Hong Ha

Liqi Wu

Wei Lei

Daping Yao

Xi Cen

David Maxwell Gage

Michael Anthony Stolfi

Byunghoon Yoon

Guojun Liu

Zhibo Yuan

Nitin K Ingle

Joseph Michael Ranish

Wei W Wang

Philip Allan Kraus

Mark Joseph Saly

Kelvin Chan

Anantha K Subramani

Yu Lei

Sang Ho Yu

Alan A Ritchie

Xiaoxiong Yuan

Christopher S Ngai

Wenhui Wang

Jianxin Lei

Yi Xu

Andrew W Yeoh

Prashanth Kothnur

William R Johanson

Ashish Goel

Rui Li

Ismail T Emesh

Ben-Li Sheu

David Michael Thompson

Lequn Liu

Tejinder Singh

Lanlan Zhong

Kishor Kumar Kalathiparambil

Yong Yang

Wenting Hou

Chunming Zhou

Byeong Chan Lee

Gang Shen

Winsor Lam

Sree Rangasai Kesapragada

Tom S Choi

Thomas Anthony Empante

Sang-heum Kim

Sudarsan Srinivasan

Methods for depositing a metal contact stack on a substrate are described. The metal stack includes a metal cap layer and a molybdenum conductor layer. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

Low resistivity metal contact stack

Methods of depositing a metal film are discussed. A metal film is formed on the bottom of feature having a metal bottom and dielectric sidewalls. Formation of the metal film comprises exposure to a metal precursor and an alkyl halide catalyst while the substrate is maintained at a deposition temperature. The metal precursor has a decomposition temperature above the deposition temperature. The alkyl halide comprises carbon and halogen, and the halogen comprises bromine or iodine.

Gap fill methods using catalyzed deposition

Methods open etch stop layers in an integrated environment along with metallization processes. In some embodiments, a method for opening an etch stop layer (ESL) prior to metallization may include etching the ESL with an anisotropic process using direct plasma to form helium ions that are configured to roughen the ESL for a first duration of approximately 10 seconds to approximately 30 seconds, forming aluminum fluoride on the ESL using remote plasma and nitrogen trifluoride gas for a second duration of approximately 10 seconds to approximately 30 seconds, and exposing the ESL to a gas mixture of boron trichloride, trimethylaluminum, and/or dimethylaluminum chloride at a temperature of approximately 100 degrees Celsius to approximately 350 degrees Celsius to remove aluminum fluoride from the ESL and a portion of a material of the ESL for a third duration of approximately 30 seconds to approximately 60 seconds.

Methods for removing etch stop layers

Organometallic precursors and methods of depositing high purity metal films are discussed. Some embodiments utilize a method comprising exposing a substrate surface to an organometallic precursor comprising one or more of molybdenum (Mo), tungsten (W), osmium (Os), technetium (Tc), manganese (Mn), rhenium (Re) or ruthenium (Ru), and an iodine-containing reactant comprising a species having a formula RI, where R is one or more of a C-Calkyl, C-Ccycloalkyl, C-Calkenyl, or C-Calkynyl group, I is an iodine group and x is in a range of 1 to 4 to form a carbon-less iodine-containing metal film. Some embodiments advantageously provide methods of forming metal films having low carbon content (e.g., having greater than or equal to 95% metal species on an atomic basis), without using an oxidizing agent or a reductant.

Method of depositing metal films

Apparatus and methods to provide electronic devices comprising tungsten film stacks are provided. A tungsten liner formed by physical vapor deposition is filled with a tungsten film formed by chemical vapor deposition directly over the tungsten liner.

Low resistivity tungsten film and method of manufacture

Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.

Methods for copper doped hybrid metallization for line and via

Methods and apparatus for processing a substrate is provided herein. For example, a method for processing a substrate comprises depositing a silicide layer within a feature defined in a layer on a substrate, forming one of a metal liner layer or a metal seed layer atop the silicide layer within the feature via depositing at least one of molybdenum (Mo) or tungsten (W) using physical vapor deposition, and depositing Mo using at least one of chemical vapor deposition or atomic layer deposition atop the at least one of the metal liner layer or the metal seed layer, without vacuum break.

Methods and apparatus for processing a substrate

Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate may be pre-cleaned. A ruthenium silicide (RuSi) layer is selectively deposited on the p transistor. A titanium silicide (TiSi) layer is formed on the n transistor and the p transistor. An optional barrier layer may be formed on the titanium silicide (TiSi) layer. The method may be performed in a processing chamber without breaking vacuum.

Dual silicide process using ruthenium silicide

Methods and apparatus for processing substrates are disclosed. In some embodiments, a process chamber for processing a substrate includes: a body having an interior volume and a target to be sputtered, the interior volume including a central portion and a peripheral portion; a substrate support disposed in the interior volume opposite the target and having a support surface configured to support the substrate; a collimator disposed in the interior volume between the target and the substrate support; a first magnet disposed about the body proximate the collimator; a second magnet disposed about the body above the support surface and entirely below the collimator and spaced vertically below the first magnet; and a third magnet disposed about the body and spaced vertically between the first magnet and the second magnet. The first, second, and third magnets are configured to generate respective magnetic fields to redistribute ions over the substrate.

Methods and apparatus for controlling ion fraction in physical vapor deposition processes

Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

Low resistivity DRAM buried word line stack

Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1X feature and at least one wider than 1X feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1X feature and at least one wider than 1X feature; the first metal material is reflowed such that the at least one 1X feature is filled with the first metal material and the at least one wider than 1X feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1X feature is filled with the second metal material.

Methods and apparatus for forming dual metal interconnects

Method for selectively oxidizing the dielectric surface of a substrate surface comprising a dielectric surface and a metal surface are discussed. Method for cleaning a substrate surface comprising a dielectric surface and a metal surface are also discussed. The disclosed methods oxidize the dielectric surface and/or clean the substrate surface using a plasma generated from hydrogen gas and oxygen gas. The disclosed method may be performed in a single step without the use of separate competing oxidation and reduction reactions. The disclosed methods may be performed at a constant temperature and/or within a single processing chamber.

Selective oxidation and simplified pre-clean

Embodiments disclosed herein generally relate to methods of depositing a plurality of layers. A doped copper seed layer is deposited in a plurality of feature definitions in a device structure. A first copper seed layer is deposited and then the first copper seed layer is doped to form a doped copper seed layer, or a doped copper seed layer is deposited directly. The doped copper seed layer leads to increased flowability, reducing poor step coverage, overhang, and voids in the copper layer.

Method of depositing multilayer stack including copper over features of a device structure

Growing community of inventors

San Jose, CA, United States of America

Joung Joo Lee