Intel Corporation

José González

Antonio González

Grigorios Magklis

Pedro Chaparro Monferrer

Qiong Cai

Fernando Latorre

Pedro Chappero Monferrer

A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.

Thread migration to improve power efficiency in a parallel processing environment

A device having multiple cores executes an algorithm to control Thin-Film Thermoelectric Coolers (TFTEC) that employ the Peltier effect to remove heat from the various cores of the multi-core processor. The algorithms may combine Thread Migration (TM) and Dynamic Voltage/Frequency Scaling (DVFS) to provide Dynamic Thermal Management (DTM) and TFTEC control.

Microarchitecture controller for thin-film thermoelectric cooling

A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

Frequency and voltage scaling architecture

A technique for allocating register resources within a microprocessor. More particularly, embodiments of the invention pertain to a register allocation technique within a microprocessor for multiple-threads of instructions or groups of micro-operations ('uops').

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Terrassa, Spain

José González