International Business Machines Corporation

Joshua W Knight

Philip George Emma

James H Pomerene

Rudolph N Rechtschaffen

Frank J Sparacio

Thomas R Puzak

Harry M Yudenfriend

David Darden Chambliss

John Glenn Thompson

James Alan Ruddy

Steven Jay Greenspan

David B Emmes

Ronald K Kreuzenstein

Alan Michael Webb

John L Czukkermann

Roger E Bonsteel

John J Lee

Juliet C Candee

James R Robinson

Luis Alfonso Lastras-Montano

Charles Franklin Webb

Ashish Jagmohan

Kevin Patrick McAuliffe

Nicholas C Matsakis

Keith N Langston

A James Van Norstrand, Jr

Juilet C Candee

James H Po Merene

A multi-mainframe system problem determination method includes receiving, in a first computing system, a data collection trigger, coordinating, in the first computing system, synchronized diagnostic data collection with a second computing system, and delivering the diagnostic data to a storage medium.

Problem determination in a hybrid environment

A multi-mainframe system problem determination method includes recording, in a first computing system, diagnostic data, receiving, in the first computing system, a data collection trigger, responsive to the data collection trigger, coordinating, in the first computing system, synchronized collection of recorded diagnostic data with a second computing system and delivering collected diagnostic data to a storage medium.

A multi-mainframe operating system serialization method can include receiving, in a first computing system, a request to access a data set on behalf of a first peer application, sending, in the first computing system, a notification to a second peer application to obtain a normal enqueue, in response to the second peer application obtaining the normal enqueue, obtaining, in the first computing system, a first rider enqueue for the data set and sending, in the first computing system, a communication to peer instances to obtain additional rider enqueues for the data set, the additional rider enqueues corresponding to the first rider enqueue.

Serialization of access to data in multi-mainframe computing environments

A heterogeneous computing system includes a first server module having a first operating system, a second server module communicatively coupled to the first server module, the second server module having a second operating system dissimilar to the first operating system, a data set accessible by the first server module and the second server module; and a process residing on the first server module, the process configured to grant access to the second server module, from the first server module, to the data set.

Access control in a hybrid environment

A method for receiving a data stream that includes data samples, each data sample having one of a plurality of actual values. For each data sample in the data stream, a first index in a dictionary is selected. The dictionary includes indices corresponding to each of the plurality of actual values. The first index corresponds to an actual value of the data sample. A predicted value of the data sample is generated in response to previously received data samples in the data stream and to a prediction algorithm. A second index in the dictionary that corresponds to an actual value in the dictionary that is closest to the value of the predicted value is selected. The difference between the first index and the second index is calculated and compressed. The compressed difference between the first index and the second index is then output. This process is performed for each data sample in the data stream.

Lossless compression of high nominal-range data

A system for porting code from a native platform to a non-native platform is provided which utilizes a non-native, platform-specific layer of code and a platform-neutral layer of code. The platform-neutral layer substantially emulates the native platform of ported code and provides a platform-neutral interface to the ported code. Together, the platform-specific layer and the platform-neutral layer provide an execution environment in which the ported code operates as a kernel extension of the non-native platform. The platform-neutral layer of the execution environment is portable to other non-native platforms so that code can be ported to another non-native platform by replacing the platform-specific layer with a customized platform-specific layer, which is adapted to the other non-native platform.

System and program product for porting code utilizing a portable execution environment

A system and program product for facilitating computing-environment control of a resource to be accessed by existing program code is provided which includes transparently replacing an uncontrolled resource referenced by existing program code with a resource controlled by a computing environment. The protocol also includes transparently interposing at least one resource management service of the computing environment between the existing program code and the resource controlled by the computing environment, wherein the at least one resource management service provides computing-environment control of the resource to be accessed by the existing program code. The replacing of the uncontrolled resource prevents the existing program code from directly accessing the resource.

System and program product for providing computing-environment control of a resource to be accessed by program code

A method of facilitating computing-environment control of a resource to be accessed by existing program code is provided which includes transparently replacing an uncontrolled resource referenced by existing program code with a resource controlled by a computing environment. The method also includes transparently interposing at least one resource management service of the computing environment between the existing program code and the resource controlled by the computing environment, wherein the at least one resource management service provides computing-environment control of the resource to be accessed by the existing program code. The replacing of the uncontrolled resource prevents the existing program code from directly accessing the resource.

Method for providing computing-environment control of a resource to be accessed by program code

A method of porting code from a native platform to a non-native platform is provided which utilizes a non-native, platform-specific layer of code and a platform-neutral layer of code. The platform-neutral layer substantially emulates the native platform of ported code and provides a platform-neutral interface to the ported code. Together, the platform-specific layer and the platform-neutral layer provide an execution environment in which the ported code operates as a kernel extension of the non-native platform. The platform-neutral layer of the execution environment is portable to other non-native platforms so that code can be ported to another non-native platform by replacing the platform-specific layer with a customized platform-specific layer, which is adapted to the other non-native platform.

Method, system and program product for porting code utilizing a portable execution environment

In a cache-to-memory interface, a means and method for timesharing a single bus to allow the concurrent processing of multiple misses. The multiplicity of misses can arise from a single processor if that processor has a nonblocking cache and/or does speculative prefetching, or it can arise from a multiplicity of processors in a shared-bus configuration.

Method for enabling concurrent misses in a cache memory

A computer processing system includes a first memory that stores instructions belonging to a first instruction set architecture and a second memory that stores instructions belonging to a second instruction set architecture. An instruction buffer is coupled to the first and second memories, for storing instructions that are executed by a processor unit. The system operates in one of two modes. In a first mode, instructions are fetched from the first memory into the instruction buffer according to data stored in a first branch history table. In the second mode, instructions are fetched from the second memory into the instruction buffer according to data stored in a second branch history table. The first instruction set architecture may be system level instructions and the second instruction set architecture may be millicode instructions that, for example, define a complex system level instruction and/or emulate a third instruction set architecture.

Computer processing unit employing a separate millicode branch history

A method for addressing data in a cache unit which has a plurality of congruence classes, following a failure which disables one or more of the congruence classes in the cache unit. A plurality of synonym classes are established. A subset of the congruence classes is assigned to each of the synonym classes. Any disabled congruence classes are identified. The synonym class to which the disabled congruence class belongs is identified. An alternate congruence class is selected which belongs to the same synonym class as the disabled congruence class. When a request is received by the cache to store a line of data into the disabled congruence class, the line is stored into the alternate congruence class in response to the request.

Cache remapping using synonym classes

System and method for predicting a multiplicity of future branches simultaneously (parallel) from an executing program, to enable the simultaneous fetching of multiple disjoint program segments. Additionally, the present invention detects divergence of incorrect branch predictions and provides correction for such divergence without penalty. By predicting an entire sequence of branches in parallel, the present invention removes restrictions that decoding of multiple instructions in a superscalar environment must be limited to a single branch group. As a result, the speed of today's superscalar processors can be significantly increased. The present invention includes three main embodiments: (1) the first embodiment is directed to a simplex multibranch prediction device, that can predict a plurality of branch groups in one cycle and provide early detection of wrong predictions; (2) the second embodiments is directed to a duplex multibranch prediction device that can detect divergence in a predicted stream, and provide redirection (correction) within the stream; and (3) the third embodiment is directed to an n-plex multibranch prediction device, that can predict n multiplicity of branch predictions simultaneously and provide an early detection of wrong predictions as well as correction of wrong predictions.

Simultaneous prediction of multiple branches for superscalar processing

A multi-prediction branch prediction mechanism predicts each conditional branch at least twice, first during the instruction-fetch phase of the pipeline and then again during the decode phase of the pipeline. The mechanism uses at least two different branch prediction mechanisms, each a separate and independent mechanism from the other. A set of rules are used to resolve those instances as to when the predictions differ.

Multi-prediction branch prediction mechanism

A digital computer includes a main and an auxiliary pipeline processor which are configured to concurrently execute contiguous groups of instructions taken from a single instruction sequence. The instructions in a sequence may be divided into groups by using either taken-branch instructions or certain instructions which may change the contents of the general purpose registers as group delimiters. Both methods of grouping the instructions use a branch history table to predict the sequence in which the instructions will be executed.

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Mohegan Lake, NY, United States of America

Joshua W Knight