Qualcomm Incorporated

Qualcomm Innovation Center, Inc.

Joshua Stubbs

Andrew James Frantz

Sean Sweeney

Robert Nicholson Gibson

Dianne D Horn

Hee Jun Park

Norman S Gargash

Young Hoon Kang

Aravind Bhaskara

Gabriel A Watkins

Zhurang Zhao

Inho Hwang

Kiran Bhagwat

Michael Tipton

Grady L Caraway

Yiran Li

Bohuslav Rychlik

Moinul H Khan

Matthew Levi Severson

Mark Michael Schaffer

Christopher Kong Yee Chun

Jaya Prakash Subramaniam Ganasan

Serag Gadelrab

Dipti Ranjan Pal

Tauseef Kazi

Vinod Chamarty

Edwin Jose

R Nicholson Gibson

Vinod Vijayarajan

Simon Booth

Philip T Mueller, Jr

Cristian Duroiu

Rohan Desai

Tracy A Ulmer

Phil Joseph Bostley, Iii

Kris Tiri

Kumar Kanti Ghosh

Sumant Madhav Paranjpe

Jyotirmoy Das

Chandan Agarwalla

Andrew Torchalski

Nilanjan Banerjee

Viswanathan Kumaragurubaran

Thomas Tang

Pavan Kumar Chilamkurthi

Andrew J Frantz

Systems, methods, and computer-readable media are provided for camera dynamic voting to optimize fast sensor mode power. In some examples, a computing device can obtain, based on performing dynamic voting, a plurality of votes associated with a plurality of components sharing a power source. The computing device can determine a voting result based on the plurality of votes. The computing device can increase or decreasing a clock rate and a voltage for the power source based on the voting result to produce an updated clock rate and an updated voltage. The computing device can then apply the updated clock rate and the updated voltage to an image processor.

Camera dynamic voting to optimize fast sensor mode power

Various dynamic voltage and frequency scaling (DVFS) techniques can optimize the high voltage residency of a device containing multiple processing cores that share a voltage rail. The DVFS techniques described herein can reduce the high voltage residency (duration) of the voltage rail by aligning the high frequency duration of multiple cores sharing the same voltage rail.

Ruler-follower dynamic voltage and frequency scaling schemes for integrated circuit components

Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.

Two-stage dynamic power supply voltage adjustment

Various embodiments include methods and devices for implementing progressive flush of a cache memory of a computing device. Various embodiments may include determining an activity state of a region of the cache memory, issuing a start cache memory flush command in response to determining that the activity state of the region is idle, flushing the region in response to the start cache memory flush command, determining that the activity state of the region is active, issuing an abort cache memory flush command in response to determining that the activity state of the region is active, and aborting flushing the region in response to the abort cache memory flush command.

Progressive flush of cache memory

A method and system for optimizing a core voltage level of a portable computing device ('PCD') and enhancing frequency performance of individual subcomponents are disclosed. A plurality of voltage values is determined for a plurality of subcomponents within the PCD. Next, a reduced set of voltage values may be calculated with a voltage aggregator based on the plurality of voltage values. An optimized voltage level for a shared power domain may then be determined by a voltage optimizer within the PCD from the reduced set of voltage values. A shared power domain may then be set to the optimized voltage level. Subsequently, an operating frequency of each subcomponent may be optimized with a frequency performance enhancer based on the optimized voltage level. An optimal power collapse duration may also be calculated by the frequency performance enhancer and set for each subcomponent from the optimal frequency.

Method and system for optimizing a core voltage level and enhancing frequency performance of individual subcomponents for reducing power consumption within a PCD

A method and system for optimizing a core voltage level of a portable computing device ('PCD') and enhancing frequency performance of individual subcomponents are disclosed. A plurality of voltage values for a plurality of subsystems is determined. At least one subsystem is a multiplexed subsystem. Next, a reduced set of voltage values is calculated based on the plurality of voltage values and an optimized voltage level is determined for a shared power domain. The shared power domain is subsequently set to the optimized voltage level. If the optimized voltage level is determined to exceed a required voltage level for the at least one multiplexed subsystem when it is running the plurality of processing engines, a subset of the plurality of processing engines may be identified to process a workload of the multiplexed system at a more efficient level of power consumption than the full plurality of processing engines.

A method for selectively scrambling data within a memory associated with a computing device based on data tagging. The computing device may define security domains that are protected. Data generated by an application may be packaged as a data bus transaction having tagging information describing the application and/or the data. The data bus transaction may be transmitted over a bus of the computing device to a memory, such as internal memory, where the computing device may compare the tagging information to stored information describing security domains. When the data is determined to be protected based on the tagging information, the computing device may perform scrambling operations on the data. In an aspect, the tagging information may describe a virtual machine used to execute various applications on a processor. In another aspect, the tagging information may define destination memory addresses or content protection bit values.

Method and devices for selective RAM scrambling

A method and system for managing sleep states of a portable computing device are described. They include maintaining a sleep set of resource states and an active set of resource states in memory. A request may be issued for a processor to enter into a sleep state. This causes a controller to review a trigger set to determine if a shut down condition for the processor matches one or more conditions listed in the trigger set. Each trigger set may comprise a 'trigger event' that may allow a controller to select a specific resource set which is desired by a particular processor based on a trigger event detected by a system power manager. If a trigger set matches a shut down condition, then switching states of one or more resources in accordance with the sleep set may be made by the controller without using a software handshake.

Method and system for rapid entry into and for rapid exiting from sleep states for processors of a portable computing device

Resource state sets corresponding to the application states are maintained in memory. A request may be issued for a processor operating in a first application state corresponding to the first resource state set to transition to a second application state corresponding to the second resource state set. A start time to begin transitioning resources to states indicated in the second resource state set is scheduled based upon an estimated amount of processing time to complete transitioning. A process is begun by which the states of resources are switched from states indicated by the first resource state set to states indicated by the second resource state set. Scheduling the process to begin at a time that allows the process to be completed just in time for the resource states to be immediately available to the processor upon entering the second application state helps minimize adverse effects of resource latency.

System for minimizing resource latency between processor application states in a portable computing device by scheduling resource state set transitions

Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.

Arbitrating bus transactions on a communications bus based on bus device health information and related power management

A start time to begin transitioning resources to states indicated in the second resource state set is scheduled based upon an estimated amount of processing time to complete transitioning the resources. At a scheduled start time, a process starts in which the states of one or more resources are switched from states indicated by the first resource state set to states indicated by the second resource state set. Scheduling the process of transitioning resource states to begin at a time that allows the process to be completed just in time for the resource states to be immediately available to the processor upon entering the second application state helps minimize adverse effects of resource latency. This calculation for the time that the process should be completed just in time may be enhanced when system states and transitions between states are measured accurately and stored in memory of the portable computing device.

Conserving power through work load estimation for a portable computing device using scheduled resource set transitions

A method and system for managing requests among resources within a portable computing device include a scheduler receiving data from a client for scheduling a plurality of requests. Each request identifies at least one resource and a requested deadline. Next, data from the client is stored by the scheduler in a database. The scheduler then determines times and a sequence for processing the requests based on requested deadlines in the requests and based on current states of resources within the portable computing device. The scheduler then communicates the requests to the resources at the determined times and according to the determined sequence. The scheduler, at its discretion, may schedule a request after its requested deadline in response to receiving a new request command from a client. The scheduler may allow a sleep set corresponding to a sleep processor state to power off a processor.

Method and system for scheduling requests in a portable computing device

A method and system for dynamically managing a bus within a portable computing device ('PCD') are described. The method and system include monitoring software requests with a bus manager. The bus manager determines if a software request needs to be converted into at least one of an instantaneous bandwidth value and an average bandwidth value. The bus manager then converts the software requests into these two types of values as needed. The bus manager calculates a sum of average bandwidth values across all software requests in the PCD. With these values, the bus manager may dynamically adjust settings of the bus based on instantaneous or near instantaneous demands from the master devices. This dynamic adjustment of the bus settings may afford more power savings for the PCD during low loads or during sleep states.

Method and system for dynamically managing a bus of a portable computing device

A method and system for managing sleep states of one or more interrupt controllers of processors contained within a portable computing device are described. The method includes a processor defining wake-up interrupt settings in a storage device contained within the portable computing device. This storage device may comprise message random access memory ('RAM'). After wake-up settings have been established in message RAM, a processor may generate an alert that the wake-up settings in the message RAM have been defined. Next, a controller reviews the wake-up interrupt settings in the message RAM for a plurality of interrupt controllers that correspond with a plurality of processors contained within the portable computing device. The controller merges the wake-up settings in the message RAM and then sends the merged wake-up settings to an always-on power manager ('APM'). The APM is responsible for issuing signals to place interrupt controllers of processors into a sleep state.

Method and system for managing sleep states of interrupt controllers in a portable computing device

Growing community of inventors

Longmont, CO, United States of America

Joshua Stubbs