Freescale Semiconductor,inc.

Motorola Corporation

Other

Nxp USA, Inc.

Joshua Siegel

Hector Adrian Sanchez

James Andrew Welker

Jose M Alvarez

Carmine Nicoletta

Khoi Mai

Michael Zimin

Chai-Chin Chao

A resonance avoidance system including a resonance avoidance controller configured to insert a delay between sequential transactions on a communication interface separated by an inactive period to avoid stimulating a power distribution network resonance. The resonance avoidance controller may be configured to insert the delay by delaying a second transaction from being driven onto the communication interface after a first transaction in which the delay is sufficient to avoid stimulating the power distribution network resonance. The delay may be inserted by delaying a driver from driving the second transaction by the sufficient delay. The conflict may be detected between first and second commands in a command queue, in which the delay may be inserted by inserting no operation commands between the commands in the command queue. Operational timing values may be stored that are used to detect resonant frequency conflicts.

System and method of controlling communication interface to avoid power distribution resonance conflict

An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state. The circuit also includes clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the data rate clock is provided as the filtered data rate clock while the clock enable is the first logic state. The circuit also includes a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data.

Mechanism for data generation in data processing systems

A band gap reference circuit including a band gap reference generator having an output for providing a reference voltage and a startup circuit for controlling current provided to the band gap reference generator when activated. The startup circuit includes a turnoff circuit having an output to deactivate the startup circuit to not control current to the band gap reference generator based on a voltage of the output of the band gap reference generator. The turnoff circuit includes an inverter having a first transistor of a first conductivity type in series with a second transistor of a second conductivity type opposite the first conductivity type. The startup circuit includes a body bias circuit connected to a body of the first transistor to provide a voltage differential between the body of the first transistor and a source terminal of the first transistor.

Bandgap reference circuit with startup circuit and method of operation

An amplifying circuit has an offset calibration mode and a normal mode. The amplifying circuit includes an amplifier having a non-inverting input and an inverting input for receiving, during the normal mode, a first input signal and a second input signal and an output for providing a high speed output signal, wherein the first input signal is a reference voltage or a high speed signal and the second input signal is a high speed signal. The amplifying circuit further includes a first transmission gate and a second transmission gate coupled in series between the non-inverting input and an inverting input that are enabled during the offset calibration mode. A benefit of this approach is that capacitance between the inverting and non-inverting inputs is reduced by the first and second transmission gates being in series. There is further benefit in reducing this capacitance by having each transmission gate receive an enable signal from a different source.

Amplifying circuit with offset compensation

Components of a memory controller are calibrated in a select sequence to compensate for variances in skew and signal level variations. The offset bias of the receiver of the I/O cell and the termination resistance of the I/O cell are calibrated. The duty cycles of the transmit path and receive path associated with the I/O cell can be calibrated using the calibrated receiver. In one aspect, the driver of the I/O cell can be calibrated prior to calibrating the receiver. Performing the calibration processes of the memory controller in one of the particular sequences described herein improves the timing budgets for the signaling conducted by the memory controller.

Memory controller calibration

An output buffer translates digital input signals which toggle between ground and V.sub.DDL to signals which toggle between ground and V.sub.DDH. The technology dielectric breakdown voltage limit is less than the magnitude of V.sub.DDH, such that use of a traditional output stage would subject transistors' dielectrics to voltages which exceed their dielectric breakdown limit, and would thus be damaged. Predrive circuits (40, 50) control output stage (70) transistors' (72, 78) gates, and voltage dropping circuits control output stage (70) transistors (74, 76). These control signals are generated specifically to maximize output stage transistor drive strengths, thereby minimizing output stage size. Output buffer functions when V.sub.DDL =V.sub.DDH, and its performance is V.sub.DDL independent. Temperature compensation is incorporated into the output buffer by deliberately offsetting temperature effects on output stage transistor drive strengths. Desired performance and temperature compensation are accomplished without subjecting any dielectrics to voltages which exceed the technology dielectric breakdown limit.

Digital output buffer for multiple voltage system

Output buffer (100) translates input signals from one voltage range to a second voltage range. The second voltage range may be identical to the first range or may be greater. The particular range is programmable by one of several ways. This feature makes output buffer especially suitable for use in devices which must be compatible with two voltage ranges. Output buffer uses a bias generator (110) to limit the voltage across the gate oxide of its various transistors to a level which is consistent with the first voltage range.

Method and output buffer with programmable bias to accommodate multiple

Level shifting circuit (36) utilizes self-timed pulse generators (40, 46) to provide a series of pulses in response to an input signal. The pulses are used to create a pulse of specified duration at a predetermined voltage level at first and second nodes (44, 45). In response to the predetermined pulses, shifted inverters (50, 52) provide a voltage output of either V.sub.DDH or V.sub.DDL, one of two different voltages which exist in a system utilizing the level shifter (36). In one form, level shifting circuit (36) may be used in an output buffer (60) to interface an integrated circuit designed to operate at a low supply voltage with additional integrated circuits operating at a higher supply voltage which could damage the gate oxide of the transistors in the low supply voltage integrated circuit.

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Austin, TX, United States of America

Joshua Siegel