Asana, Inc.

Sifive, Inc.

Apple Inc.

Marvell International Limited

Joshua R Smith

Scott Alexander Smith

David Braginsky

Anne DuBois

Cliff Chang

John Stahl, Jr

Krste Asanovic

Andrew Waterman

Brian Robert Mestan

Pradeep Kanapathipillai

Warren Menezes

Zachary Isaac Millman

Phillips Smith Peter, Iii

Caleb David Wang

Megan Maureen Daly

Systems and methods to manage access to assets of a computer environment based on user and asset grouping are described herein. Exemplary implementations may perform one or more of: manage asset groups associated with one or more assets of a computer environment; manage user groups associated with individual asset groups; assign users to user groups to cause access characteristics of associated assets to be granted to users; enable and/or disable individual access characteristics based on assigned ones of the user groups; and/or other operations.

Systems and methods to manage access to assets of a computer environment based on user and asset grouping

Systems and methods are disclosed for fetch stage handling of indirect jumps in a processor pipeline. For example, a method includes detecting a sequence of instructions fetched by a processor core, wherein the sequence of instructions includes a first instruction, with a result that depends on an immediate field of the first instruction and a program counter value, followed by a second instruction that is an indirect jump instruction; responsive to detection of the sequence of instructions, preventing an indirect jump target predictor circuit from generating a target address prediction for the second instruction; and, responsive to detection of the sequence of instructions, determining a target address for the second instruction before the first instruction is issued to an execution stage of a pipeline of the processor core.

Fetch stage handling of indirect jumps in a processor pipeline

A method is provided to produce a custom calendar user interface (UI) display on an electronic device display screen comprising: providing a search query to a user device; sending the search query over the network to a server system; receiving over the network by one or more user devices from a server system, information that identifies one or more code objects that match the search query; using the identified one or more identified code objects by the one or more user devices to generate one or more visual content items within a calendar user interface (UI) grid display on their device display screens.

Client side system and method for search backed calendar user interface

Systems and methods are disclosed for duplicate detection for register renaming. For example, a method includes checking a map table for duplicates of a first physical register, wherein the map table stores entries that each map an architectural register of an instruction set architecture to a physical register of a microarchitecture and a duplicate is two or more architectural registers that are mapped to a same physical register; and, responsive to a duplicate of the first physical register in the map table, preventing the first physical register from being added to a free list upon retirement of an instruction that renames an architectural register that was previously mapped to the first physical register to a different physical register, wherein the free list stores entries that indicate which physical registers are available for renaming.

Duplicate detection for register renaming

A system and method for efficiently performing maintenance on a cache. In various embodiments, control logic in a cache controller or elsewhere receives an indication for invalidating a range of virtual-to-physical mappings in a given translation lookaside buffer (TLB). The logic determines a first latency to invalidate entries of the TLB based on a number of addresses in the range and a number of supported page sizes simultaneously stored in the TLB. The logic determines a second latency based on a number of entries in the TLB. If the first latency is greater, then the logic traverses through each TLB entry and invalidates TLB entries storing a virtual address within the range. If the first latency is smaller, then the logic traverses through each address in the range and invalidates TLB entries storing a virtual address within the range.

Translation lookaside buffer invalidation by range

A circuit includes an instruction scheduling circuit and an instruction buffer including entries. The entries each include an instruction, a validity indication, and an attribute. The instruction scheduling circuit partitions the entries into first sets, determines second sets by reordering the entries of each first set according to their attributes, determines a set ordering for the first sets according to a function of their attributes, and selects, based on the set ordering, instructions from the second sets. A process for selecting instructions to issue receives entries, each entry including an instruction, a validity indications, and an attribute. The process partitions the entries into first sets, determines second sets by reordering the entries of each first set according to their attributes, determines a set ordering for first sets according to a function of the attributes of their entries, and selects, based on the set ordering, instructions from the second sets.

Selection of instructions to be issued

A method is provided to produce a custom calendar user interface for display on an electronic device display screen comprising: receiving over a network code objects adapted for use to generate visual content items on the different user device display screens; receiving over the network from a user device, receiving a search query; identifying one or more respective received code objects that match the received search query; and sending over the network to one or more user devices, information indicating the identified matching code objects.

Growing community of inventors

San Francisco, CA, United States of America

Joshua R Smith