Lsi Corporation

Joshua P Sinykin

Jeffrey K Whitt

Eugene Saghi

Paul Jeffrey Smith

Steven F Faulhaber

Matthew Freel

Brian A Day

William K Petty

Gabriel Leandro Romero

Erik Paulsen

Douglas J Saxon

Sreedeepti Reddy

Methods and structure for correlating multiple sets of test output signals in time are provided. The structure includes an integrated circuit comprising a block of circuitry that generates internal operational signals. The circuit also comprises a test multiplexer (MUX) hierarchy that selects subsets of the internal signals and applies the subsets to a testing element. A clock generator generates a clock signal for the selected signals. A test logic timer receives the clock signal and increments a counter value, and applies the counter value to the testing element. An event detector resets the counter value upon detection of an event, such that a first subset of the internal signals acquired from the test MUX hierarchy acquired responsive to detection of a first instance of the event may be correlated in time with a second subset of the internal signals acquired responsive to detection of a second instance of the event.

Methods and structure for correlating multiple test outputs of an integrated circuit acquired during separate instances of an event

Methods and structure are provided for routing internal operational signals of a circuit for output via an external interface. The structure includes an integrated circuit. The integrated circuit comprises a block of circuitry components operable to generate internal operational signals for performing designated functions during normal operation of the circuit, a control unit, a test signal routing hierarchy, and an external interface. The test signal routing hierarchy is coupled to receive the internal operational signals and controllably selects the internal operational signals for acquisition and applies them to the control unit. The external interface provides communications between the integrated circuit and an external device during normal operation of the integrated circuit. The control unit receives the selected internal operational signals from the test signal routing hierarchy, and applies the selected internal operational signals to the external interface during normal operation of the integrated circuit.

Methods and structure for utilizing external interfaces used during normal operation of a circuit to output test signals

Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals.

Methods and structure for correlation of test signals routed using different signaling pathways

Methods and structure for providing methods and structure for recovering errors in a hardware controller after an overwrite event, such as the detection of another error. In this regard, a link layer of the hardware controller is configured with a register that persistently stores errors until a processor can address them. The link layer is adapted to establish a connection between an initiator and a target and detect errors associated with the connection. As each detected error is overwritten by a subsequently detected error, the link layer register persistently stores the detected errors associated with the connection for recovery after the detected error has been overwritten in the link layer at least until the error can be handled.

Methods and structure for storing errors for error recovery in a hardware controller

An expander device and method for transmitting serial input/output (SIO) data between an initiator device and a plurality of target devices. The expander device includes a processor/controller configured to receive a master data stream from an initiator device and to transmit a returning master data stream to the initiator device. The expander device includes a plurality of target master ports coupled to the processor/controller and configured to transmit split data streams to corresponding target devices coupled thereto and to receive returning split data streams from the target devices. The processor/controller splits the master data stream, based on its data, into a plurality of split data streams, and directs the split data streams to the target master ports based on the data in the split data streams. The processor/controller also assembles a plurality of returning split data streams into the returning master data stream and transmits the returning master data stream to the initiator device.

Serial input output (SIO) port expansion apparatus and method

Apparatus and method for managing power consumption of circuits within a Serial Attached SCSI (SAS) device. A SAS device having a plurality of PHY logic circuits includes a queue manager and a power manager. The queue manager is operable to determine a current workload based on queued entries for the plurality of PHY logic circuits. Based on the current workload, the power manager is operable to set identified ones of the plurality of PHY logic circuits into a low power mode. In some embodiments, PHY logic circuits may be restored to full power operation responsive to changes in the current workload and/or responsive to receipt of a signal from another SAS device coupled to the SAS device. In other embodiments the power manager is further operable to manage power consumption of link and/or DMA logic circuits of the SAS device.

Methods and apparatus for load-based power management of PHY logic circuits of a SAS device based upon a current workload

Methods and systems for customizing information in a memory associated with a SAS host bus adapter ('HBA'). A SAS HBA typically includes a memory component that stores information common to all SAS HBA's manufactured by a particular vendor (e.g., common instructions and data). In addition, each HBA memory component typically includes some information unique to each HBA (e.g., board trace number, SAS address, configuration page, boot record, etc.). Features and aspects hereof permit pre-programmed memory components to be integrated with a SAS HBA to eliminate a step to program an assembled HBA through a specialized, one-time interaction to add required unique information. Thus a manufacturer may simply integrate a pre-programmed memory component to an otherwise completed HBA assembly to complete the product manufacturing without need for a special programming step. Or a design or test engineer may simply replace a memory component to change unique information on the HBA.

Methods and systems for integrating unique information in SAS interface components

Methods and structures within a SAS domain for automated tuning performance of a coupled pair of transceivers. In one aspect hereof, control registers of a transmitting transceiver coupled to a receiving transceiver are adjusted to a plurality of distinct combinations of settings. For each distinct setting, a test pattern may be transmitted from the transmitting transceiver to the receiving transceiver. Status registers of the transmitting transceiver and of the receiving transceiver may be read to identify errors in the transmission. Identified errors are counted for each for distinct setting of the control registers to determine a preferred setting to best tune operation of the transceiver pair. The testing may be performed by any SAS initiator device or SAS expander acting as an initiator and may be performed on any coupled pair of transceiver in the SAS domain.

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Shrewsbury, MA, United States of America

Joshua P Sinykin