International Business Machines Corporation

Joshua P Hernandez

Benjiman L Goodman

Timothy Michael Skergan

Samuel I Ward

Linton B Ward, Jr

Daniel W Cervantes

Robert Benjamin Gass

Tung Nang Pham

A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.

System and method for power reduction through power aware latch weighting of complex sub-circuits

A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.

System and method for power reduction through power aware latch weighting

A method, system and computer program product for performing real-time LBIST diagnostics of IC devices. During LBIST, stump data and identifiers of test cycles are saved in the IC device-under-test (DUT). If compressed stump data does not match a pre-defined coded value (i.e., 'signature' of the test cycle), the saved stump data and an identifier of the failed test cycle are preserved, otherwise the determination is made the DUT passed the test cycle. Identifiers and stump of the failed test cycles are used to analyze errors, including virtually non-reproducible errors.

Techniques for logic built-in self-test diagnostics of integrated circuit devices

A method to reduce logic built in self test manufacturing test time of integrated circuits, comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array locally disposed on an integrated circuit, each of the plurality of test seeds is associated with a set of LBIST control information; sending the plurality of test seeds from the locally accessible on-chip memory array repetitively into a pseudo-random pattern generator one at a time during an LBIST operation being under the control from the set of LBIST control information; generating random bit streams serially into a plurality of parallel shift registers of the integrated circuit through the use of the plurality of test seeds; and performing a logic built-in self test on a plurality of logic blocks in the integrated circuit to detect defects within the integrated circuit.

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Paige, TX, United States of America

Joshua P Hernandez