Apple Inc.

Joshua P De Cesare

Michael R Smith

Dallas Blake De Atley

Anand Dalal

Brijesh Tripathi

John Andrew Wright

Timothy John Millet

Bernard Joseph Semeria

Manu Gulati

Erik P Machnicki

Shane J Keil

Jonathan Jay Andrews

Gilbert H Herbeck

Jung Wook Cho

Michael J Smith

Shantonu Sen

Matthew Reda

Keith Alan Cox

Timothy R Paaske

Jeffrey R Wilcox

Christopher P Tann

Kenneth Christian Dyke

Arthur L Spence

Derek R Kumar

Jerry Hauck

Guy Cote

Yafei Bi

Mohammad Bagher Vahid Far

Alexei Elias Kosut

Mahesh B Chappalli

Jeffrey Alan Bush

Simon M Douglas

Ilie Garbacea

Venu Madhav Duggineni

Lei He

Michael W Murphy

Vanessa Cristina Heppolette

Mir Bahram Ghaderi

Hardik K Doshi

Malcolm D Gray

Hyuck-Jae Lee

Xeno S Kovah

Corey T Kallenberg

Nikolaj Schlej

Kevin H Alderfer

Paolo Sacchetto

Michael F Culbert

Peter F Holland

Joseph P Bratt

Gerard Richard Williams

Wade Benson

Conrad Sauerwald

Nathaniel C Begeman

David James Williamson

Pradeep Kanapathipillai

Shih-Chieh Wen

John H Kelm

Weihua Mao

Peter G Soderquist

Toshi Takayanagi

Ezekiel T Runyon

In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

System on a chip with always-on processor

In an embodiment, a system on a chip (SOC) includes a component that remains powered when a central processing unit (CPU) processor and a memory controller of the SOC are powered off. The component may include a sensor capture unit to capture audio samples from an audio detector circuit and write them to a memory of the component. A processor of the component may be configured to search the audio samples for a predetermined pattern during a time when the CPU processor and the memory controller are powered down. In some embodiments, based on the audio samples filling to a threshold level in the memory of the component and a lack of detection of the predetermined pattern, the component is configured to wake up the memory controller and a path to the memory controller in order to write the audio sample to a memory controlled by the memory controller.

System on a chip with always-on component with powered-down configurations to process audio samples

A method and apparatus for performing a secure boot of a computer system is disclosed. A computer system according to the disclosure includes an auxiliary processor and a main processor. The boot process includes initially booting the auxiliary processor. The auxiliary processor includes a non-volatile memory storing boot code for the main processor. The auxiliary processor may perform a verification of the boot code. Subsequent to verifying the boot code, the main processor may be released from a reset state. Once the main processor is no longer in the reset state, the boot code may be provided thereto. Thereafter, the boot procedure may continue with the main processor executing the boot code.

Method and apparatus for secure system boot

This application relates to techniques that adjust the sleep states of a computing device based on user proximity detection procedures. The technique includes detecting a first pattern, using a first subset of sensors of one or more sensors coupled to the computing device, to determine if the object is proximate to the computing device. Provided the first pattern is not indicative of the object being proximate to the computing device, the technique detects a second pattern, using a second subset of sensors of the one or more sensors, to determine if the object is proximate to the computing device. Furthermore, provided either the first pattern or the second pattern is indicative of the object being proximate to the computing device and provided a first portion of a computer system within the computing device is operating within a low-power sleep state, the technique causes the first portion to enter into a high-power sleep state.

Techniques for adjusting computing device sleep states using onboard sensors and learned user behaviors

Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals, the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value. If the timestamp is earlier than the global timer value, the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory. The display control unit may then apply the updates of the frame configuration set to its pixel processing elements. After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display.

Timestamp based display update mechanism

Systems, methods, and apparatus to transition a display device between operating modes using a single dedicated pin of a circuit connected to the display device. The dedicated pin can receive a packet signal corresponding to an operating mode for the display device, and the circuit can thereafter cause the display device to transition into the desired operating mode in response to receiving the packet signal. The operating mode can be a low power on mode where an interface connected to the circuit is deactivated and at least some circuitry of the display device is throttled or powered off. The display device can be driven in an all black state while in the low power on mode, thereby allowing the display device to more quickly transition out of the low power on mode compared to when the display device is completely off.

Low power display on mode for a display device

A method and an apparatus for establishing an operating environment by certifying a code image received from a host over a communication link are described. The code image may be digitally signed through a central authority server. Certification of the code image may be determined by a fingerprint embedded within a secure storage area such as a ROM (read only memory) of the portable device based on a public key certification process. A certified code image may be assigned a hash signature to be stored in a storage of the portable device. An operating environment of the portable device may be established after executing the certified code.

Securely recovering a computing device

System on a chip with fast wake from sleep

Techniques are disclosed relating to data storage. In various embodiments, a computing device includes first and second processors and memory having stored therein a first encrypted operating system executable by the first processor and a second encrypted operating system executable by the second processor. The computing device also includes a secure circuit configured to receive, via a first mailbox mechanism of the secure circuit, a first request from the first processor for a first cryptographic key usable to decrypt the first operating system. The secure circuit is further configured to receive, via a second mailbox mechanism of the secure circuit, a second request from the second processor for a second cryptographic key usable to decrypt the second operating system, and to provide the first and second cryptographic keys.

Multiple mailbox secure circuit

A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

Deferred inter-processor interrupts

In an embodiment, processors may have associated special purpose registers (SPRs) such as model specific registers (MSRs), used to communicate IPIs between the processors. In an embodiment, several types of IPIs may be defined, such as one or more of an immediate type, a deferred type, a retract type, and/or a non-waking type. The immediate IPI may be delivered and may cause the target processor to interrupt in response to receipt of the IPI. The deferred IPI may be delivered within a defined time limit, and not necessarily on receipt by the target processor. The retract IPI may cause a previously transmitted IPI to be cancelled (if it has not already caused the target processor to interrupt). A non-waking IPI may not cause the target processor to wake if it is asleep, but may be delivered when the target processor is awakened for another reason.

Intracluster and intercluster interprocessor interrupts including a retract interrupt that causes a previous interrupt to be canceled

Growing community of inventors

Campbell, CA, United States of America

Joshua P De Cesare