The University of Texas System

Arizona State University

Carnegie Mellon University

The University of Arizona

Episys Science, Inc.

Joshua Mack

Daniel W Bliss

Chaitali Chakrabarti

Nirmal Kumbhare

Samet Egemen Arda

Ali Akoglu

Anish Krishnakumar

Radu Marculescu

Ahmet Goksoy

Ali Oliver Akoglu

Anderson Sartor

Umit Ogras

Sumit Mandal

Hierarchical and lightweight imitation learning (IL) for power management of embedded systems-on-chip (SoCs), also referred to herein as HiLITE, is provided. Modern SoCs use dynamic power management (DPM) techniques to improve energy efficiency. However, existing techniques are unable to efficiently adapt the runtime decisions considering multiple objectives (e.g., energy and real-time requirements) simultaneously on heterogeneous platforms. To address this need, embodiments described herein propose HiLITE, a hierarchical IL framework that maximizes energy efficiency while satisfying soft real-time constraints on embedded SoCs. This approach first trains DPM policies using IL; then, it applies a regression policy at runtime to minimize deadline misses. HiLITE improves the energy-delay product by 40% on average, and reduces deadline misses by up to 76%, compared to state-of-the-art approaches. In addition, the trained policies not only achieve high accuracy, but also have negligible prediction time overhead and small memory footprint.

HiLITE: hierarchical and lightweight imitation learning for power management of embedded SoCs

A novel design for conflict free address generation mechanism is provided for reading data from Block RAM (BRAM) into a Fast Fourier Transform (FFT) module and writing back the processed data back to the BRAM. Also, a novel way of reducing a memory footprint by reducing a twiddle factor table size by taking an advantage of the symmetry property of twiddle factors is presented. Further, additional architecture-specific optimizations are provided, which involve a design of deeply pipelined butterfly modules and the BRAM accesses, parallel butterfly modules for a single FFT block and parallel FFT lane implementation.

Apparatus and method of a scalable and reconfigurable fast fourier transform

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Tucson, AZ, United States of America

Joshua Mack