Xilinx, Inc.

Joshua M Silver

David A Harrison

Soren T Soe

Hua Xue

Sholeh Diba

A method for programming complex programmable logic devices (CPLDs) to implement a logic function, whereby user-designated locked equations of the logic function are mapped into the macrocells of a function block, and then undesignated (non-locked) equations are mapped into the remaining macrocells. The method shifts product terms between the macrocells to adjust the placement arrangement of the mapped equations, thereby obtaining a placement arrangement which is both valid and meets user-defined timing constraints.

Method for mapping product terms in a complex programmable logic device

A method for programming programmable logic devices (PLDs) having multiple function block types to implement a logic function, whereby the logic function is mapped into one of the function block types before being mapped into the remaining function block types. In one embodiment, a PLD containing both 'fast' function blocks (FFBs) and 'high density' function blocks (HDFBs) are programmed such that the FFBs are programmed prior to the HDFBs. This method maximizes the overall speed of an implemented logic function.

Method for programming complex PLD having more than one function block

A method for programming PLDs in which feedback signals are alternately programmed to produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by multiple concurrent switching events. The method is applied to CPLDs having interconnect matrices including input lines and output lines connected by programmable connection circuits, and having macrocells connected at their output to one of the input lines via first selective inversion circuits, and connected at their input to the output lines via second selective inversion circuits. The method includes selecting a first macrocell generating a feedback signal which is routed to a second macrocell, generating a random command to either invert or not-invert the feedback signal, and, if the generated random command is to invert the feedback signal, programming the associated first selective inversion circuit to invert the feedback signal as it enters the interconnect matrix, and programming the associated second selective signal inversion circuit to re-invert the inverted feedback signal transmitted from the interconnect matrix to the second macrocell.

Method for reducing switching noise in a programmable logic device

A method for placing a logic function into the function blocks of a complex programmable logic device (CPLD) to maintain the same input/output pin locations after the logic function is subsequently modified by a user. The method utilizes a weighting function to assign portions of the logic function to the function blocks such that sufficient resources are available in each function block to implement subsequent modifications to the logic function without changing the originally-assigned input and output pin locations. For each portion of the logic function, the weighting function is employed to identify the function block which implements the portion while maximizing the available resources in all of the function blocks. If a particular equation cannot be placed, the method utilizes a corrective measure such as fitting refinement, buffering and logic reformation to place the equation. If the equation still cannot be placed, the weighting function is altered, thereby changing the criteria by which logic portions are assigned to the function blocks. The placement method is then repeated with the altered weighting function.

Programmable logic device placement method utilizing weighting function

A multiplexer for a programmable logic device (PLD) includes a control line decode circuit that substantially reduces the number of control lines necessary to program a multiplexer. Each multiplexer input line is programmably connected to at least three output lines to increase the number of routing options. A TTL buffer circuit located at the output of the multiplexer provides the user with various output signal options, whereas a word line driver coupled to the TTL buffer circuit increases signal drive. Local feedback signals are provided to the multiplexer to increase PLD functionality. Signals from the I/O pads are routed directly to the multiplexer rather than the UIM, thereby improving PLD speed. Moreover, using the multiplexer minimizes the number of input lines because the UIM is still available for routing connections. Therefore, the present invention provides both fast cycle time and fast multiple level logic.

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Sunnyvale, CA, United States of America

Joshua M Silver