Microchip Technology Inc.

Joshua M Conner

Joseph W Triece

James H Grosbach

Michael I Catherwood

Randy L Yach

Rodney J Drake

Sumit K Mitra

Brian E Boles

Edward Brian Boles

Darrel Johansen

Michael S Pyska

James Grosbach

Rodney Jay Drake

Darrel Ray Johansen

Michael Pyska

Fast access of a memory having a stack uses an address bit, a stack pointer, and fast access random access memory ('RAM'). When a first address mode is used in conjunction with the address bit and the stack pointer, the location of the access RAM can be shifted in order to achieve an index of a literal offset address mode.

Method and system for fast access to stack memory

A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used to some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.

Microcontroller instruction set

A processor processes a variable cycle interrupt disable instruction DISI X is provided. The instruction disables interrupt processing for a variable number of processor cycles corresponding to the value specified by the instruction operand X. The DISI X instruction may be strategically used by programmers to prevent interrupts from being taken during certain intervals within a program.

Variable cycle interrupt disabling

A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require special purpose instructions or two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memory space and data memory space, but provides the capability to map at least a portion of the program memory space to the data memory space. This allows most program instructions that are processed to obtain the speed advantages of simultaneous program instruction and data access, yet provides a means to access program memory resident data without special purpose instructions. It also allows program memory space and data memory space to be expanded externally to the processor using only one external memory device that includes both program instructions and data. The processor includes a program memory space operable to store program instructions and data, a data memory space operable to store data, and mapping circuitry operable to map at least a portion of the program memory space to the data memory space. The program memory space may be internal to the processor. The processor may further comprise a page register operable to specify a location of the program memory space that is mapped to the data memory space.

Modified Harvard architecture processor having program memory space mapped to data memory space

A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.

Dynamically reconfigurable data space

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Apache Junction, AZ, United States of America

Joshua M Conner