Intel Corporation

Joshua Keener

John Heck

Harel Frish

Hari Mahalingam

Haisheng Rong

Sergei L Sochava

Ling Liao

Michael E Favaro

Stefan Meister

Wesley Harrison

Randal Appleton

Sean McCargar

Shane Yerkes

Silicon photonic integrated circuit (PIC) on a multi-zone semiconductor on insulator (SOI) substrate having at least a first zone and a second zone. Various optical devices of the PIC may be located above certain substrate zones that are most suitable. A first length of a photonic waveguide structure comprises the crystalline silicon and is within the first zone, while a second length of the waveguide structure is within the second zone. Within a first zone, the crystalline silicon layer is spaced apart from an underlying substrate material by a first thickness of dielectric material. Within the second zone, the crystalline silicon layer is spaced apart from the underlying substrate material by a second thickness of the dielectric material.

Silicon photonic integrated circuits on substrates with structured insulators having specific thicknesses in separate zones

Embodiments of the present disclosure are directed to low numerical aperture (NA) optical couplers, or spot size converters, that include a lateral taper section and/or a vertical adiabatic taper section. In embodiments, the optical couplers may be positioned on a silicon substrate proximate to V-grooves within the substrate to contain optical fibers to self-align and to couple with the optical couplers. Other embodiments may be described and/or claimed.

Multi-layer silicon photonics apparatus

Growing community of inventors

Albuquerque, NM, United States of America

Joshua Keener