L3harris Technologies, Inc.

L-3 Communications Corporation

Joshua D Gunn

Ryan W Hinton

Edwin J Hemphill

Thomas R Giallorenzi

Samuel Charles Kingston

Radivoje Zarubica

David G Landon

David W Thorson

Scott C Smedley

Kim J Olszewski

A decoding method implemented at a decoder. The method includes determining a current channel realized reliability metric for each symbol in a received sequence of symbols. The current channel realized reliability metrics of the symbols are then sorted to identify a predetermined number of most reliable independent bits in the sequence. A set of one or more bit-flip patterns are then enumerated based on the current channel realized reliability metrics of the predetermined number of the most reliable independent bits in the sequence. The set of bit-flip patterns or a subset thereof are then applied to a received vector corresponding to the sequence of symbols to decode a codeword.

Complexity ordered statistic decoding using improved bit flipping pattern ordering

A variable width barrel shifter. The variable width barrel shifter includes a first barrel shifter configured to receive a data vector of width M as input. The variable width barrel shifter further includes a second barrel shifter configured to receive the data vector of width M as input. The variable width barrel shifter includes an element-wise multiplexer coupled to the first and second barrel shifters. The element-wise multiplexer is configured to provide a shifted output of the data vector of width M by including a first portion of output from the second barrel shifter and a second portion of output from the first barrel shifter.

Variable width barrel shifter

Signal processing to compensate for gain control output spikes caused by steps in a digital step attenuator. A method includes receiving a changing power input signal at a receiver. The method includes determining that a change in power of the input signal will cause a step attenuator to change its attenuation in a step of a predetermined amount. The method further includes based on determining that the change in power of the input signal will cause a digital step attenuator to change its attenuation in a step of a predetermined amount, causing a variable attenuator to change its attenuation by an amount related to the predetermined amount at a time coinciding with a time when the step attenuator changes its attenuation by the predetermined amount. The method further includes outputting a gain-controlled output signal resulting from applying the step attenuator and the variable attenuator to the changing power input signal.

Joint stepped overlapping hysteresis gain control

A method for mitigating interference in a frequency hopping channel system based on codeword metrics obtained during decoding of codewords. The method includes decoding a plurality of codewords using a particular error control coding method. Each of the plurality of codewords includes portions received from plurality of channels in the frequency hopping channel system. For each decoded codeword, one or more codeword metrics are obtained based on the cost of correcting errors during decoding of the plurality of codewords. Based on the codeword metrics, one or more channel metrics are inferred. Based on the inferred one or more channel metrics, a reliability metric of a particular channel is reduced, or incoming symbols received from the particular channel are ignored during decoding.

Frequency hopping interference detection using decoder codeword metrics

Iterative signal processing. At communication hardware, a signal is received from a transmission medium. The signal has characteristics that obscure data or a signal of interest in the signal. The signal is processed at a first signal processor, which is an iterative processor that performs signal processing in cycles whereby successive cycles: improve the performance of processing of the processor itself over previous cycles, or improve the output from the processor. The signal is processed at one or more second signal processors. Extrinsic data, with respect to the first signal processor is produced as a result. The extrinsic data is provided to the first signal processor and used to counter the effects of the data or signal of interest being obscured in the signal, while the first signal processor is intracycle of a first processing cycle.

Partial update sharing in joint LDPC decoding and ancillary processors

A forward error correction (FEC) decoder is configured to find an alignment of a code block in a data stream by attempting to fully or partially decode one or more data windows of a predetermined size in the data stream. The predetermined size is a size of each codeword. The FEC decoder selects a first data window of the predetermined size, attempts to decode the first data window based on a particular error control coding method, and determines whether a valid codeword can be identified by attempting to decode the first data window. In response to determining that a valid codeword can be identified, the FEC decoder determines that an alignment of the codeword with the first data window is found. Otherwise, the FEC decoder selects a second data window of the predetermined size and attempts to decode the second data window.

Alignment detection by full and partial FEC decoding

The presence of a hidden signal can be detected efficiently using frequency domain multiplication. A detector system can be employed to search for a hidden signal across a wide spectrum in real time. The detector system can divide multiple antenna inputs into a series of blocks and then convert these blocks to the frequency domain possibly in a parallel fashion. Corresponding blocks from each input can then be conjugate multiplied, and the results of this conjugate multiplication can then be averaged over time. If a signal is hidden in the inputs, this averaging will reduce the noise floor thereby revealing the presence of the hidden signal at a particular frequency.

Efficiently detecting presence of a hidden signal using frequency domain multiplication

An LDPC decoder includes a check node processor. The check node processor is configured to implement an n-degree check node, where n is a predetermined number. The degree of a check node is the number of edges coupled to the check node. The LDPC decoder also includes a plurality of n time division multiplexers coupled to the check node processor to couple different edge connection input values to the check node processor at different times so as to allow the check node processor to be time division multiplexed for use in implementing different check nodes with the same check node processor. Each of the multiplexers is configured to provide no more than one edge connection input value to the check node processor at any given time. Each edge connection is used to implement an edge into a check node.

Time shared protograph LDPC decoder

A multi-mode parameter adaptation module can comprise different modes for generating parameters to minimize an error between an output of an adaptive processor and an ideal output of the adaptive processor. A mode control module can monitor a performance signal p indicative of an operating condition a receiver of which the adaptive processor is a part. Upon detecting a change condition form the performance signal p, the mode control module can change the operating mode of the parameter adaptation module to suit the current operating condition.

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Farmington, UT, United States of America

Joshua D Gunn