Cadence Design Systems, Inc.

Joshua Alexander Baudhuin

Henry K Yu

Hui Xu

Roland Ruehl

Timothy Rosek

Elias Lee Fallon

Regis R Colwell

Harindranath Parameswaran

Yinnie Lee

Sanjib Ghosh

Pardeep Juneja

Harsh Deshmane

Anjna Khanna

Simon Simonian

Yu Liu

Hongzhou Liu

Karun Sharma

Sandipan Ghosh

Sabra Rossman

Gary Matsunami

Steven Riley

Ron Pyke

Juno Lin

Allen You

Chris (Shyh-Chang) Lin

Rahaprian Premavathi Mudiarasan

Jiulong Zhang

Thomas Richards

Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic design library including a plurality of design rules. Embodiments may include generating a routing graph, based upon, at least in part, the plurality of design rules, wherein the routing graph is a virtual representation of all of the available routing space for all routing layers associated with an electronic design. Embodiments may further include dynamically updating the routing graph at a graphical user interface, based upon, at least in part, a creation of a routing segment or a via at the graphical user interface.

System and method for routing in an electronic design

Disclosed are techniques for implementing routing aware floorplanning or placement for an electronic design. These techniques preprocess an electronic design and a plurality of inputs for a floorplanner or placer, identify a tentative location for inserting a block comprising one or more pins into a floorplan or placement layout, snap the block to a legal location based at least in part upon one or more characteristics of the one or more pins or one or more pseudo-pins, and update the floorplan or placement layout with one or more geometric routes based in part or in whole upon the legal location.

Method, system, and computer program product for implementing routing aware placement or floor planning for an electronic design

Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems. In embodiments, the color based track systems can include irregularly spaced and non-uniform width colored tracks. These and other embodiments include a methodology to automatically generate a track pattern for an integrated circuit design that satisfies both design constraints and user inputs. Various alternatives for identifying starting points in the design for automatically generating track patterns are possible.

Generating a colored track pattern of non-uniform width from a sparse set of tracks

Disclosed encompasses method, system, computer program product for implementing interactive checking of constraints. Various embodiments bridge schematic design environment and layout environment with a binder mapping process and utilize connectivity information from the schematic design to identify constraint violations early in the physical design stage. The method identifies or creates a layout and identifies or generates an object for a modification process. The method may take snapshot(s) of the design database or may use one or more logs for restoring the design database. The method then identifies or creates scratch pad(s) and performs modification process on the object to generate a change. The method uses scratch pad(s) and trigger(s) to perform constraint checking during the modification process to provide interactive feedback in response to the modification process before committing the change to the persistent database.

Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraints

Disclosed are methods and systems for implementing constraint and connectivity aware physical designs. The method or system provides a connectivity-aware environment to implement electronic designs. For example, the method interactively determines whether an electronic design complies with various constraints by using connectivity information in a nearly real-time manner while the electronic design is being created in some embodiments. The method or system uses the connectivity information provided by a connectivity engine or specified by designers to present feedback to a user as to whether a newly created object or a newly modified object complies or violates certain relevant constraints in an interactive manner or in nearly real-time without having to perform such constraints checking in batch mode. The method further enables one to implement electronic designs by using connectivity information without performing extraction on layouts or rebuilding nets.

Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness

Disclosed are methods and systems for providing a constraint-driven environment for implementing a physical design of an electronic circuit with automatic snapping. In some embodiments, the method identifies or creates an incomplete layout. The method identifies an object and constraints for the object. The method then identifies an approximate position for the object in the layout and automatically snaps the object to a drop location based on the approximate position while complying with relevant constraint(s). The method may further align an object with another object with some spacing in between in some embodiments. The method may also perform automatic layer-to-layer snapping between two sets of objects such as cell instances, each having at least one object on multiple layers.

Methods, systems, and articles of manufacture for implementing a physical design of an electronic circuit with automatic snapping

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Portland, OR, United States of America

Joshua Alexander Baudhuin