Analog Devices,inc.

Joshua A Kablotsky

Yosef Stein

James M Wilson

Christopher Mayer

Gregory M Yukna

Haim Primo

Colm J Prendergast

Fabian Lis

Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.

Compute units using local luts to reduce pipeline stalls

An instruction-based parallel median filtering processor and method sorts in parallel each combination of pairs of inputs into greater and lesser values; determines from that sorting the minimum, maximum and median filter values of the inputs; processes one of those values and provides the processed value as an input; and applies an instruction for providing one of the values to the processing step, and at least one other instruction for enabling indication of at least one of the maximum, minimum, median filter values.

Instruction-based parallel median filtering

Lookup table addressing of a set of lookup tables in an external memory is achieved by: transferring a data word from a compute unit to an input register in a data address generator; providing in at least one deposit-increment index register in the data address generator including a table base field for identifying the location of the set of tables in memory, and a displacement field; and depositing a section of the data word into a displacement field in the index register for identifying the location of a specific entry in the tables.

Lookup table addressing system and method

Pipelined digital signal processor

In various embodiments, the invention pertains to systems for acoustic beamforming that include one or more speaker membranes, such as, for example, a continuous ribbon membrane, and several independently addressable drivers. Moreover, certain embodiments relate to methods for beamforming with improved directionality.

Systems and methods for acoustic beamforming using discrete or continuous speaker arrays

A Galois field divider engine and method inputs a 1 and a first Galois field element to a Galois field reciprocal generator to obtain an output, multiplies in the Galois field reciprocal generator the first Galois field element by the output of the Galois field reciprocal generator for predicting the modulo remainder of the square of the polynomial product of an irreducible polynomial m&#x2212;2 times to obtain the reciprocal of the first Galois field element, and multiplies the reciprocal element by a second Galois field element for predicting the quotient of the two Galois field elements in m cycles; in a broader sense the invention includes a compound Galois field engine for performing a succession of Galois field linear transforms on a succession of polynomial inputs to obtain an ultimate output where each input except the first is the output of the previous Galois field linear transform.

Compound Galois field engine and Galois field divider and square root engine and method

A compute unit with an internal bit FIFO circuit includes at least one data register, a lookup table, a configuration register including FIFO base address, length and read/write mode fields for configuring a portion of the lookup table as a bit FIFO circuit and a read/write pointer register responsive to an instruction having a lookup table identification field, length of bits field and register extract/deposit field for selectively transferring in a single cycle between the FIFO circuit and the data register a bit field of specified length.

Compute unit with an internal bit FIFO circuit

Finite impulse response filtering is achieved by broadcasting to at least one compute unit an instruction having a plurality of data samples, a conditional field associated with each compute unit, and a set of operator values for operating on each data sample; providing a function of each the data sample in accordance with an associated set of operator values identified by the conditional field; and combining the functions to obtain an intermediate finite impulse response of the data samples.

Method and apparatus for accelerating processing of adaptive finite impulse response filtering

Accelerating processing of a non-sequential instruction stream on a processor with multiple compute units by broadcasting to a plurality of compute units a generic instruction stream derived from a sequence of instructions; the generic instruction stream including an index section and a compute section; applying the index section to localized data stored in each compute unit to select one of a plurality of stored local parameter sets; and applying in each compute unit the selected set of parameters to the local data according to the compute section to produce each compute unit's localized solution to the generic instruction.

Method and apparatus for accelerating processing of a non-sequential instruction stream on a processor with multiple compute units

A method and apparatus are provided for imaging three-dimensional scenes and objects by detecting reflections from emitted sequences of electromagnetic radiation. At least one transmitter is provided for emitting a sequence of electromagnetic radiation, and at least three sensors are provided for detecting radiation reflected from the scene and objects being imaged. Signals based on the detected radiation are used, together with spatial information of the transmitters and sensors, to calculate reflectivity coefficients for points of interest in the scene. Velocity vectors associated with moving objects within the scene can also be determined based on the rate of change of the phase differences between the emitted and reflected radiations.

Method and apparatus for three-dimensional imaging

An improved programmable compute system and method for executing an H.264 binary decode symbol using only a single instruction and two compute units is achieved by providing not just one rLPS value but all four next possible rLPS values of the current context next state so that there is no delay initially while calculating the correct rLPS because all four are present and any one can be chosen; further all the parameters e.g. value, range, context, and rLPS can be served by only two available 32 bit registers by generating, locally, the MSP ninth bit, of range based on the fact that the range is normalized to a known value in the MSB.

Simplified programmable compute system for executing an H.264 binary decode symbol instruction

A condensed Galois field computing system including a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and a Galois field linear transformer circuit for applying an irreducible polynomial of power n to the product including a partial result generator responsive to terms of power n and greater in the product for providing a folded partial result and a Galois field adder for condensing the folded partial result and the terms less than power n in the product to obtain Galois field transformer of power n of the product.

Condensed Galois field computing system

A compute system for executing an h.264 binary decode symbol instruction including a first compute unit having a range normalization circuit and an rLPS update circuit, and operating in a first mode responsive to current rLPS, range, value and current context to generate the next normalized range and next rLPS for the current context; a second compute unit including a value update circuit, a context update circuit, and value normalization circuit responsive to current rLPS, range value and current context to obtain the output bit, normalized value and the updated current context; and a third compute unit or said first compute unit operating in a second mode including a range circuit and a next context rLPS circuit responsive to rLPS range, value and next context to obtain a next context rLPS value.

Programmable compute system for executing an H.264 binary decode symbol instruction

A processing system supporting a secure mode of operation is disclosed. The processing system includes a read-only hardware key that is only accessible in secure mode.

Programmable processor supporting secure mode

An advanced encryption standard (AES) engine with real time S-box generation includes a Galois field multiplier system in a first mode responsive to a first data block for generating an AES selection (S-box) function by executing the multiplicative increase in GF(2) and applying an affine over GF(2) transformation to obtain a subbyte transformation; and a shift register system for transforming the subbyte transformation to obtain a shift row transformation; the Galois field multiplier system is responsive in a second mode to the shift row transformation to obtain a mix column transformation and add a round key for generating in real time an advanced encryption standard cipher function of the first data block.

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Sharon, MA, United States of America

Joshua A Kablotsky