Taiwan Semiconductor Manufacturing Comp. Ltd.

Josh J H Feng

Ru-Gun Liu

Wen-Chun Huang

Tsong-Hua Ou

Ying-Chou Cheng

Cheng-Lung Tsai

Chih-Ming Lai

Tsai-Sheng Gau

Ming-Hui Chih

Cheng-Cheng Kuo

Chia-Ping Chiang

Yu-Po Tang

Cheng-Kun Tsai

Jeng-Shiun Ho

Wei-Long Wang

Luke Lo

Bing-Syun Yeh

The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout.

Customized patterning modulation and optimization

The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node.

Practical approach to layout migration

The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.

Dissection splitting with optical proximity correction and mask rule check enforcement

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Lotung, Taiwan

Josh J H Feng