U.S. Philips Corporation

Koninklijke Philips Corporation N.V.

Nxp B.v.

Josephus Antonius Huisken

Franciscus A Van De Laar

Johannus Theodorus Matheus Hubertus Dielissen

Kim Phan Le

Jose De Jesus Pineda De Gyvez

Andries Pieter Hekstra

Hans Marc Bert Boeve

Johannes De Wilde

Franciscus Gerardus Maria De Jong

Jozef L Van Meerbergen

Nico Frits Benschop

Franciscus P Beenker

Jozef Louis Van Meerbergen

Rudi J Stans

Antoine Delaruelle

Luc L Matterne

Marco J Bekooij

Antoine DeLaruelle

A sensor for contactlessly detecting currents, has a sensor element having a magnetic tunnel junction (MTJ), and detection circuitry, the sensor element having a resistance which varies with the magnetic field, and the detection circuitry is arranged to detect a tunnel current flowing through the tunnel junction. The sensor element may share an MTJ stack with memory elements. Also it can provide easy integration with next generation CMOS processes, including MRAM technology, be more compact, and use less power. Solutions for increasing sensitivity of the sensor, such as providing a flux concentrator, and for generating higher magnetic fields with a same current, such as forming L-shaped conductor elements, are given. The greater sensitivity enables less post processing to be used, to save power for applications such as mobile devices. Applications include current sensors, built-in current sensors, and IDDQ and IDDT testing, even for next generation CMOS processes.

High sensitivity magnetic built-in current sensor

A decoding method for decoding Low-Density Parity Check codes in transmission and recording systems includes a running minimum loop with the following iterative acts: reading a reliability value from the input sequence of input reliability values; comparing the reliability value with a stored value; and overwriting the stored value with the reliability value if the reliability value is smaller than the stored value.

Running minimum message passing LDPC decoding

A turbo decoder system () for decoding turbo coded bits, is provided with a system input () and a plurality of turbo decoders (--n) each having a turbo decoder input (--n). The plurality of turbo decoders (--n) is arranged in parallel, and the system () is further provided with an allocating device () coupled between the system input () and the turbo decoder inputs (--n) for dynamically allocating the turbo coded bits to one of the turbo decoders (-n).

Turbo decoder system comprising parallel decoders

Global Position System (GPS) receiver for receiving and processing GPS signals includes cicuitry for receiving and processing Digital Audio Broadcast (DAB) signals. To realize simultaneous processing of both DAB and GPS signals, the receiver is provided with a receiver front-end, a mixer stage, filter, and analog-to-digital converter coupled to digital DAB and GPS signal paths. The receiver further includes a DAB signal eliminating device for selectively eliminating DAB signals from the digital GPS signal path.

GPS receiver

A DAB receiver in which a reduced time de-interleaving memory for storing metrics is used, but which still allows processing of DAB services which normally would exceed the storage capacity of the memory. This is achieved by varying the length of a stored metric, depending upon the storage capacity required, by varying the number of stored reliability bits in a metric. In this way, a trade-off can be made between storage capacity and processing quality.

Receiver de-interleaving means and a method for a reduced time

In a digital audio broadcast receiver a digital audio transmission signal is supplied to a demodulator which provides demodulation samples. The demodulation samples are de-interleaved in a first section of a de-interleaving memory. After having been de-interleaved, demodulation samples are transferred to a second section of the de-interleaving memory. This transfer is effectuated in bursts via a relatively small buffer which stores the bursts. The second section of the de-interleaving memory effectively constitutes a relatively large buffer. De-interleaved demodulations samples are regularly read from the second section and supplied as a regular stream to a Viterbi decoder by means of a relatively small first-in first-out register.

De-interleaving and buffering in one memory

When the processing circuitry of a signal processor can handle data at a faster rate than the rate of arrival of signal units to be processed, the processor is able to execute a cycle of microcodes for each arriving signal unit. To generate the cycle, the signal processor contains base address reproducing means, for in each cycle reproducing a standard sequence of successive base addresses BA(i) (i=1 . . . N). The base address reproducing means feed microcode selecting means for selecting, in step with each base address and under control of signal data received from the processing circuitry, an associated microcode address MA(i) from a repertory of microcode addresses indicated by the base address BA(i). Selection is implemented by adding each base address BA(i) to an associated index IA(i), determined in dependence on signal data received from the processing circuitry. Usually, the indices IA(i) require fewer bits than the base addresses BA(i); the indices are determined in codependence of the base address, or of a signal identifying a class to which the base address belongs. The signal data is collected from the processing circuitry via a shift register.

Addressing scheme for microcode store in a signal processor

A hardware-efficient data receiver in which the receiver digital baseband signal samples relate to the bits in the transmission signal. For each sample, a metric calculator calculates an input data element (metric) for the soft decision decoder in the receiver. The metric is a binary word of whose most significant bit (gross bit) indicates the most likely value (`0` or `1`) of a bit in the transmission signal. The other bits of the metric (reliability bits) express the reliability of this gross bit. The metric calculator has a monotonous transition function with equidistant steps between two extreme metric values (all metric bits are `0` or `1`). According to this transition function, the metric value varies as a function of the digital baseband signal sample value in a range bounded by two saturation values. The number of different sample values in this range, including the saturation values, is two to the power of an integer. Within this range, the reliability bits may readily be derived from a selected number of bits in the binary representation of a digital baseband sample.

Data receiver, method of calculating metrics, and signal processing

A modified Booth multiplier for multiplying an m-bit number X by an n-bit number Y comprises a Booth encoder for converter the number Y in groups of 3 bits which overlap by 1 bit into a series Y' of multiplication values whose number is equal to or substantially equal to half the number of bits of Y. There is also provided a multiplex circuit for forming partial products from the number X and said series Y' and a matrix configuration of full adders for adding the partial products in incremental positions. The design is such that the constituent components and the operation of the modified Booth multiplier can be tested by means of a very small number of test patterns which are generated in the Booth multiplier after application of a specific series of X,Y-values. Test patterns are generated for establishing static as well as dynamic errors in the combination formed by the Booth encoder and the multiplex circuit and also test patterns which are formed by specific partial products in order to establish static errors in the matrix configuration. In practice the modified Booth multiplier is usually constructed as a multiplier accumulator; in that case test patterns formed by partial products are also used for establishing static errors in the accumulator section.

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Eindhoven, Netherlands

Josephus Antonius Huisken