International Business Machines Corporation

Motorola Corporation

Joseph Yih Chang

Bret Ronald Olszewski

James Nolan Hardage

Jose Melanio Nunez

Thomas Albert Petersen

Paul A Reed

Charles G Wright

Hidayat Lioe

Brian J Snider

A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor of a TLB entry invalidation request, the second processor marks at least one memory referent instruction that is being processed by the second processor and invalidates a TLB entry in the TLB of the second processor. In response to receipt of a synchronization request at the second processor, the second processor indicates to the first processor that the second processor has invalidated the TLB entry if the second processor has completed processing the marked instruction. During the interval between receipt of the synchronization request and indicating to the first processor that the second processor has invalidated the TLB entry, the second processor continues to process instructions, including fetching instructions for processing. In this manner, the second processor is able to continue normal instruction processing during the process of TLB synchronization.

Data processing system and method for maintaining translation lookaside

A method and apparatus are provided for generating a ratioed clock signal. A first clock signal having a first frequency is output. At least one gating signal indicating ratio is output. In response to the first clock signal and the gating signal, a second clock signal is output. The second clock signal has a frequency that is substantially related to the first frequency by the ratio.

Apparatus and method for generating a clock in a microprocessor

A check is made to determine if a copy of a cache line is currently resident in the level-one data cache of a microprocessor system. If, in response to the check, it is determined that a copy of such cache line in fact is not currently resident, the cache line is created as the least-recently used cache line. Then, for set-associative data caches, the next used of the associative set will replace the most recently zeroed line. In this way, zeroing operations can replace only one .div. (number of associative sets) of the data cache for zeroing operations, thereby leaving the most frequently used data intact. By doing so, the data-cache is not wasted on zeroed cache lines which may be infrequently reused from the data cache, thereby significantly improving system performance. In other words the net effect is to reduce probability of data cache misses on subsequent instructions because more of the cache is thereby made available for more frequently reused data. The state of the cache is better preserved without creating performance losses exhibited by the previous technique. In a preferred embodiment, the hereinbefore described system and method is employed in systems with processors comprising substantial writeback queues and memory subsystems permitting numerous outstanding writes to be in progress, and is further employed in systems embodying cache line zero/invalidate instructions.

System and method for zeroing pages with cache line invalidate

A data processor (10) has a cache array (40) and a control unit (58) for storing a number of recently accessed data lines. If an execution unit requests a data line that is not stored in the memory cache (a miss) then the control unit will request the data from an external memory device and allocate a location in the cache array in which it will store the requested data when returned. In the depicted embodiment, the control unit first attempts to allocate an invalid one of N possible locations, where N is the set way associativity of the memory cache. If none of the ways is invalid, then the control unit uses a least recently used (LRU) algorithm to select the location. Therefore, the data cache may be non-blocking up to N times to the same set.

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Cedar Park, TX, United States of America

Joseph Yih Chang