Gi, LLC

Other

General Semiconductor, Inc.

General Instrument Corporation

General Instrument Corporation of Delaware

Joseph Y Chan

Dennis Garbis

Gregory Zakaluk

Jack Eng

Lawrence LaTerza

Willem G Einthoven

John Amato

Jun Wu

William G Einthoven

John Latza

Robert C Heller

Ali Salih

Amedeo J Granata

John E Amato

Larry Laterza

Reinhold Hirtz

Lawrence Laterza

John Sapio

Sandy Tan

Transient voltage suppressor semiconductor devices and other semiconductor devices having rigorous requirements for the diffusion and depth of impurities to produce P-N junctions can be fabricated at surprisingly low costs without sacrifice of functional characteristics by subjecting the substrate to a grinding process resulting in a surface short of polishing perfection, thereby to eliminate the time-consuming and hence costly conventional polishing operation, and then diffusing the desired impurity into the substrate from a solid impurity source.

Low cost method of fabricating transient voltage suppressor semiconductor devices or the like

Starting with a semiconductor wafer of known type including an internal, planar p-n junction parallel to major surfaces of the wafer, one of the wafer surfaces is covered with a masking layer of silicon nitride. A plurality of intersecting grooves are then sawed through the masking layer for forming a plurality of mesas having sloped walls with each mesa including a portion of the planar p-n junction having edges which intersect and are exposed by the mesa walls. The groove walls and exposed junction edges are glass encapsulated in a process including heating the wafer. The masking layers are then removed in a selective etching process not requiring a patterned etchant mask, and the now exposed silicon surfaces at the top of the mesas, as well as the opposite surface of the wafer, are metal plated. The wafer is then diced along planes through the grooves for providing individual chips each having a glass passivated mesa thereon.

Semiconductor chips having a mesa structure provided by sawing

A high voltage silicon rectifier includes a substrate portion and an epitaxial mesa portion that is a frustrum of a pyramid with a substantially square cross section and side walls that make a forty five degree angle with the substrate portion. The mesa portion includes three germanium doped layers that introduce strain to speed up recombination of charge carriers. The topography of the base region of the rectifier has a high-low junction that includes a central portion that is deeper in the mesa than the germanium-doped layers and an edge portion that is shallower in the mesa than the germanium-doped layers and forms a positive bevel angle with the tapered side walls of the mesa,

High voltage silicon diode with optimum placement of silicon-germanium

Significant reduction in the cost of fabrication of shallow junction, Schottky or similar semiconductor devices without sacrifice of functional characteristics, while at the same time achieving the advantages is achieved, after the non-polishing cleaning step is essentially performed, by subjecting the substrate to conditions which move disadvantageous factors within said substrate into a space substantially at said surface, followed by substantially removing said factor-containing space from said substrate chemical removal step, followed etching and vapor deposition steps. Although these new steps add time, and therefore cost, to the overall process, the devices under discussion when produced by known industry processes require yet more time, and involve yet more expense, so that the total process represents a substantial reduction in the cost of their manufacture while producing devices which are the equivalent or superior in electrical performance to such devices which are made by known industry processes.

Low cost method of fabricating shallow junction, Schottky semiconductor

To minimize contamination of gas flow lines and reactor surfaces from high impurity concentrations present in the CVD reactor, control of the dopant gas supply is located closely adjacent to the reactor input port and the dopant gas supply line is separately vented. First and second dopant gas supplies and a diluent gas supply are connected to branch lines which converge to form the dopant supply line. A solenoid valve is situated in the main dopant supply line as close to the input port as possible. A vent line is connected to the dopant supply line, prior to the solenoid valve. The etchant and silicon gas supplies are each connected to the reactor input by a separate supply line. The etchant and silicon gas supply lines are vented separately from the dopant gas supply line.

Gas flow system for CVD reactor

An all epitaxial process performed entirely in a CVD reactor is employed to grow epitaxial layers with accurately controlled successively low and high dopant concentrations over a heavily doped substrate, eliminating the need for a separate diffusion, even for high purity concentrations. After purging the reactor system, the heavily doped silicon substrate is 'capped' by growing two successive very thin silicon sublayers of the same conductivity type. The reactor chamber is subjected to a hydrogen purge to deplete any contaminents after each sublayer is formed. The cap sublayers form a narrow, abrupt intrinsic transition region with the substrate and become an active part of the device structure. A lightly doped epitaxial layer is grown over the 'capped' substrate so that a depletion region can be formed in the device under suitable reverse bias. A heavily doped epitaxial layer is then grown over the lightly doped epitaxial layer. The heavily doped epitaxial layer forms a contact layer and has a polarity opposite to that of the substrate.

Method for fabricating a multilayer epitaxial structure

Significant reductions in the cost of fabrication of epitaxial semiconductor devices without sacrifice of functional characteristics is achieved by eliminating the conventional but costly polishing procedure, instead subjecting the substrate to grinding, cleaning and etching processes in which the grinding removes material from the surface to a depth of at least 65 microns and the etching further removes material to a depth of about 6-10 microns, the grinding preferably being carried out in two steps, the first being a coarse step and the second being a fine step, with the rotated grinding elements dwelling at their respective last grinding positions for a short period of time. The result is the equivalent of the prior art polishing procedure which took considerably longer to carry out and which therefore was much more costly. Complementing this grinding procedure is an improved and cost effective epitaxial process utilizing a unique two-step hydrochloric gas high temperature etch and a faster growth rate process with shorter cycle steps. In addition, oxygen control and 'gettering' capabilities result in a total process improving the economics of formation of epitaxial semiconductor devices.

Low cost method of fabricating epitaxial semiconductor devices

This invention concerns itself with an improved method of producing sharply defined misfit dislocations; (MD) with a new, inexpensive method of doping these misfit dislocations with Au; with invention that a combination of Au and Pt doping in misfit dislocations is superior to any amount of Au and to some specific placements of the misfit dislocations in the device structure.

Method of growing a semiconductor material by epilaxy

An all epitaxial process performed entirely in a CVD reactor is employed to grow heavily doped layer on lightly doped layer on a heavily doped substrate, eliminating the need for separate diffusion, even for high impurity concentrations. The process starts with a heavily doped silicon substrate of carrier concentration typically greater than 1.times.10.sup.19 per cm.sup.3. To minimize outdiffusion, the substrate is 'capped' by growing very thin and heavily doped silicon layers which are depleted by hydrogen purges. A first epitaxial layer is grown over the 'capped' substrate. This layer is relatively lightly doped, having a resistivity of more than 200 ohm.cm. A second epitaxial layer is then grown over the first epitaxial layer. The second epitaxial layer has a polarity opposite to that of the substrate and is heavily doped to a resistivity of less than 0.005 ohm cm.

The all epitaxial process starts with a high resistivity silicon substrate. Alternating layers of silicon and silicon-germanium are epitaxially grown on the substrate under conditions which create a region with misfit dislocations. A low resistivity silicon layer is then grown over the region. The material is inverted such that the high resistivity layer can be used to form the base of the device. The thickness of the high resistivity layer is adjusted to equal the width of the base of the semiconductor device to be fabricated.

Method of making semiconductor devices using epitaxial techniques to

A reactor for use in a chemical vapor deposition process occurring in a radiant absorption heater system employs a vertical gas flow reaction vessel and a novel substantially solid susceptor configured as a truncated wedge. The susceptor is characterized by a high utilized area, resulting in a high wafer capacity and low power requirement.

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Kings Park, NY, United States of America

Joseph Y Chan