Promos Technologies, Inc

Other

Joseph Wu

J S Shiao

Sheng-Fen Chiu

Nien-yu Tsai

Yu-Ping Chu

Hsiao-Li Wang

Chen-Wei Chen

A new method to reduce variation in an output parameter by selection of an optimal process recipe in the manufacture of an integrated circuit device is achieved. The method may be used to reduce the array voltage threshold in a DRAM circuit by compensating the source/drain ion implantation by calculating a predicted array voltage threshold. The integrated circuit device wafer is measured to obtain a present set of process parameter values. A predicted value of an output parameter is calculated by evaluating a first equation at the present set of process parameter values. The first equation is derived from a plurality of previous sets of process parameter values and the corresponding plurality of sets of output parameter values. The difference between the predicted value of the output parameter and a target value of the output parameter is the output parameter delta. A process recipe offset is calculated by evaluating a second equation at the output parameter delta. The second equation is derived from the plurality of selectable process recipes and the plurality of corresponding output parameter values. An optimal process recipe is selected from the plurality of selectable process recipes by adding the process recipe offset to the target process recipe to compensate the output parameter and to thereby reduce the variation.

Method to reduce lot-to-lot variation of array threshold voltage in a DRAM device

A new method of forming gate conductor lines for a DRAM in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. Active areas are defined. A gate conductor layer is deposited overlying the semiconductor substrate. The gate conductor layer is patterned to form gate conductor lines. The intersections of the gate conductor lines and the active areas form DRAM transistors. Adjacent gate conductor lines are spaced a first minimum distance in critical regions and are spaced a second minimum distance in non-critical regions. The critical regions are defined as the active areas between adjacent gate conductor lines where bit line contacts are planned. The non-critical regions are defined as areas located between the critical regions and the adjacent gate conductor lines. The second minimum distance is greater than the first minimum distance to thereby decrease the aspect ratio in the non-critical regions to less than the aspect ratio in the critical regions. An insulating layer is deposited overlying the gate conductor lines and the semiconductor substrate. The insulating layer completely fills the non-critical regions without creating voids to thereby eliminate bit line contact to bit line contact shorts without affecting transistor performance.

Method to improve isolation layer fill in a DRAM array area

A semiconductor memory cell has a deep trench capacitor and a vertical transistor formed over the deep trench capacitor. The vertical transistor has a control gate electrode, a source/drain region at opposite sides of the control gate electrode, and a channel region surrounding the sidewall and top of the control gate electrode. This can increase the length of the channel region to reduce leakage current.

Memory cell having a deep trench capacitor and a vertical channel

A method for forming a bit line of a DRAM memory array is disclosed. The method comprises the steps of: forming an interlayer dielectric over the DRAM memory array; etching the interlayer dielectric to form trenches in the interlayer dielectric, the trenches collectively forming a bit line pattern and having tapered side walls; and depositing a conductive material into the trenches to form the bit line.

Etching method for reducing bit line coupling in a DRAM

A wafer ID optical sorting system includes an auto-ID reader, a manual-ID reader and a conveying device, operation of which units is controlled by a monitoring system. The auto-ID reader, connected to the monitoring system, can automatically read and identify an ID and allows the ID to be displayed on the monitoring system. The manual-ID reader, connected to the monitoring system, can fetch the ID image and allows it to be displayed on the monitoring system. The conveying device, connected to the monitoring system, can move the auto-ID reader and the manual-ID reader.

Wafer ID optical sorting system

A method of forming a planar silicon nitride layer is disclosed. The method comprises: forming a pad oxide layer; forming a first nitride layer on the pad oxide layer; forming a stop layer on the first nitride layer; forming a second nitride layer on the stop layer; performing intermediate processes that damage the second nitride layer; removing the second nitride layer; removing the stop layer such that the first nitride layer remains as the planar silicon nitride layer.

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Hsinchu, Taiwan

Joseph Wu