Intel Corporation

Other

Agere Systems Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Petroleum Fermentations N.v.

Ernie Green Industries, Inc.

Joseph Williams

Kameran Azadet

Jian-Guo Chen

Samer Lutfi Hijazi

Meng-Lin Yu

Albert Molina

Joseph H Othmer

Jeroen Leijten

Parakalan Venkataraghavan

Zoran Zivkovic

Joseph L La Mura

Steven Pinault

Jay O'Neill

Michael E Hayes

Chengzhou Li

James F Deal, Iii

Ramon Sanchez Perez

Kamran Azadet

Sanal Cheruvathery

William Gaul

Sandy Williams

Richard R Wade

Harm Peters

Todd A Sheets

James Primont

Eugene Scuteri

Paul Zazzera, Jr

David T Dougherty

John W Sansing

Hong Wan

David Dougherty

Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.

Processing pipeline with zero loop overhead

Techniques are disclosed for the use of fused vector processor instructions by a vector processor architecture. Each fused vector processor instruction may include a set of fields associated with individual vector processing instructions. The vector processor architecture may implement local buffers facilitating a single vector processor instruction to be used to execute each of the individual vector processing instructions without re-accessing vector registers between each executed individual vector processing instruction. The vector processor architecture enables less communication across the interconnection network, thereby increasing interconnection network bandwidth and the speed of computations, and decreasing power usage.

Vector processor utilizing massively fused operations

Techniques are disclosed for the use of local buffers integrated into the execution units of a vector processor architecture. The use of local buffers results in less communication across the interconnection network implemented by vector processors, and increases interconnection network bandwidth, increases the speed of computations, and decreases power usage.

Processor embedded streaming buffer

Techniques are disclosed for a vector processor architecture that enables data interpolation in accordance with multiple dimensions, such as one-, two-, and three-dimensional linear interpolation. The vector processor architecture includes a vector processor and accompanying vector addressable memory that enable a simultaneous retrieval of multiple entries in the vector addressable memory to facilitate linear interpolation calculations. The vector processor architecture vastly increases the speed in which such calculations may occur compared to conventional processing architectures. Example implementations include the calculation of digital pre-distortion (DPD) coefficients for use with radio frequency (RF) transmitter chains to support multi-band applications.

Vector processor supporting linear interpolation on multiple dimensions

A delivery drone apparatus for automatically delivering packages includes a drone body having a body cavity. A pair of landing skids is coupled to the drone body. A battery, a CPU, and a GPS are coupled within the body cavity. A transceiver is coupled within the body cavity and is in operational communication with the battery, the CPU, and the GPS. The transceiver is configured to communicate with a smartphone. At least one camera is coupled to the drone body. The camera is in operational communication with the battery, the CPU, the GPS, and the transceiver. A plurality of motors are coupled to the drone body. Each motor has a propeller and is in operational communication with the battery and the CPU. An electromagnet is coupled to the drone body. A package magnet is selectively engageable with the electromagnet and is configured to be coupled to a package.

Delivery drone apparatus

Systems, methods, and apparatuses relating to a user defined formatting instruction to configure multicast Benes network circuitry are described. In one embodiment, a processor includes a decoder to decode a single instruction into a decoded single instruction, the single instruction having fields that identify packed input data, packed control data, and a packed data destination; and an execution unit to execute the decoded single instruction to: send the packed control data to respective control inputs of a circuit that comprises an inverse butterfly circuit coupled in series to a butterfly circuit, wherein the inverse butterfly circuit comprises a first plurality of stages of multicast switches and the butterfly circuit comprises a second plurality of stages of multicast switches, read, once from storage separate from the circuit, each element of the packed input data as respective inputs of the circuit, route the packed input data through the circuit according to the packed control data, and store resultant packed data from the circuit into the packed data destination.

Apparatuses, methods, and systems for a user defined formatting instruction to configure multicast Benes network circuitry

Systems, methods, and apparatuses relating to vector processor architecture having an array of identical circuit blocks are described. In one embodiment, a processor includes a single centralized circuit comprising an instruction decoder and a controller; and a plurality of circuit slices that each comprise an arithmetic logic unit, a multiplier, a register file, a local memory, and a same plurality of logic circuits and a packed data datapath in between, wherein each circuit slice includes a physical port that provides a unique identification value that identifies a circuit slice from the other circuit slices, and the controller is to broadcast a same configuration value to the plurality of circuit slices to cause a first circuit slice to enable a first logic circuit and enable a second logic circuit of the first circuit slice based on its unique identification value and the configuration value, and cause a second circuit slice to enable a same, first logic circuit and disable a same, second logic circuit of the second circuit slice based on its unique identification value and the configuration value.

Apparatuses, methods, and systems for vector processor architecture having an array of identical circuit blocks

Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xfunction, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.

Software digital front end (SoftDFE) signal processing

A configurable generic filter hardware block and corresponding methods are provided. A configurable generic filter hardware block includes a plurality of multipliers; a plurality of adders; and one or more multiplexers. The, configurable generic filter hardware block is configured using a header data structure, and the header data structure includes a pointer to a memory location storing a plurality of input samples, a pointer to a memory location storing a plurality of output samples and a coefficient selection control value. The configurable generic filter hardware block is optionally invoked by a convolution instruction in one or more of a vector processor and a state machine. An exemplary Generic Filter Iteration loads input samples; selects coefficients; convolves the input samples and the selected coefficients and stores output samples. The header data structures are optionally stored sequentially in memory and processed in a single loop.

Configurable generic filter hardware block and methods

A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to &#x3b8;; and computing a fine corrective value using a polynomial approximation.

Digital processor having instruction set with complex exponential non-linear function

A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function.

Vector processor having instruction set with sliding window non-linear convolutional function

A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least NN-input samples; obtaining Ntime shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises Nsamples; and performing a weighted sum of the time shifted versions of the vector by a vector of Ncoefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.

Vector processor having instruction set with vector convolution function for fir filtering

A digital signal processor and method are disclosed with one or more non-linear functions using factorized polynomial interpolation. A digital signal processor evaluates a non-linear function for a value, x, by obtaining two or more values from at least one look-up table for said non-linear function that are near said value, x; and interpolating said two or more obtained values to obtain a value, y, using a factorized polynomial interpolation.

Digital signal processor with one or more non-linear functions using factorized polynomial interpolation

A digital signal processor is provided having an instruction set with an xfunction that uses a reduced look-up table. The disclosed digital signal processor evaluates an xfunction for an input value, x, by computing Log(x) in hardware; multiplying the Log(x) value by K; and determining the xfunction by applying an exponential function in hardware to a result of the multiplying step. One or more of the computation of Log(x) and the exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input value, x.

Growing community of inventors

Holmdel, NJ, United States of America

Joseph Williams