Spansion Llc.

Advanced Micro Devices Corporation

Samsung Electronics Co., Ltd.

Tokyo Electron Limited

Joseph William Wiseman

Hongyu Henry Yue

Anthony John Toprac

William S Brennan

Allen Lewis Evans

Bryon K Hance

Kelley Kyle Higgins

Brian D White

Robert Louis Dawson

Shengnian Davis Song

Suraj K Patil

A semiconductor device includes a gate electrode disposed on a fin, a gate spacer disposed on the fin and a sidewall of the gate electrode, a source/drain electrode disposed on the fin, and an air pocket structure interposed between the gate spacer and the source/drain electrode. The air pocket structure includes an air gap, a first sidewall, a top sealing, a second sidewall and a bottom sealing. The air gap is enclosed by the first sidewall, the top sealing, the second sidewall and the bottom sealing arranged in a clockwise sequence. The top sealing and the bottom sealing include the same material of an energy removable material.

Semiconductor device and method of fabricating the same

Devices and systems for insulating integrated circuits from ultraviolet ('UV') light are described. The device includes a conductive feature, a first and second UV blocking layer, a first and second insulating laver, and a conductive structure. The first insulating layer overlays the first UV blocking layer. A via opening extends through the first insulating layer and the first UV blocking layer. The second UV blocking layer overlays the first insulating laver. The second insulating layer overlays the second UV blocking layer. An interconnect trench is defined in the second insulating layer and second UV blocking layer. The conductive structure is electrically connected to the conductive feature and extends into the via opening and along the interconnect trench.

Electronic devices with ultraviolet blocking layers

A process of forming an electronic device including forming a first ultraviolet ('UV') blocking layer over a conductive feature, wherein the first UV blocking layer lies within 90 nm of the conductive structure; forming a first insulating layer over the first UV blocking layer; and patterning the first insulating layer and the first UV blocking layer to form a first opening extending to the conductive feature, wherein during the process, the first UV blocking layer is exposed to UV radiation.

Method of forming an electronic device

Methods for fabricating contacts to semiconductor structures are provided. A method comprises forming two members extending from a semiconductor substrate and separated by a portion of the substrate. First and second semiconductor devices are formed in and on the substrate and each comprise a common impurity doped region that is disposed within the portion of the substrate. A dielectric layer is deposited overlying the members, the semiconductor devices, and the common impurity doped region to a thickness such that a depression overlying the impurity doped region is formed. A fill material is deposited to substantially fill the depression and a portion of the dielectric layer is etched. A masking layer is deposited and a portion of the masking layer is removed to expose the fill material. A via is formed by etching the fill material and dielectric layer and a conductive material is deposited therein.

Methods for fabricating semiconductor devices and contacts to semiconductor devices

Methods for fabricating semiconductor structures and contacts to semiconductor structures are provided. A method comprises providing a substrate and forming a gate stack on the substrate. The gate stack is formed having a first axis. An impurity doped region is formed within the substrate adjacent to the gate stack and a dielectric layer is deposited overlying the impurity doped region. A via is etched through the dielectric layer to the impurity doped region. The via has a major axis and a minor axis that is perpendicular to and shorter than the major axis. The via is etched such that the major axis is disposed at an angle greater than zero and no greater than 90 degrees from the first axis. A conductive contact is formed within the via.

A method for manufacturing a semiconductor component using a sacrificial masking structure. A semiconductor device is formed from a semiconductor substrate and a layer of dielectric material is formed over the semiconductor substrate and the semiconductor device. The layer of dielectric material may be formed directly on the semiconductor substrate or spaced apart from the semiconductor substrate by an interlayer. Posts or protrusions having sidewalls are formed from the layer of dielectric material. An electrically insulating material that is preferably different from the layer of dielectric material is formed adjacent the sidewalls of the posts. The electrically insulating material is planarized and the posts are removed to form openings that may expose a portion of the semiconductor device or a portion of the interlayer material. An electrically conductive material is formed in the openings.

Method for manufacturing a semiconductor component

Methods and structures are provided for a dual-bit EEPROM semiconductor device. The dual-bit memory device comprises a semiconductor substrate, a tunnel oxide disposed on the semiconductor substrate and first and second spaced apart floating gates that are disposed on the tunnel oxide. An interlayer dielectric layer contacts the tunnel oxide layer at a position between the first and second spaced apart floating gates and electrically isolates the first and second spaced apart floating gates. A control gate contacts the interlayer dielectric layer between the first and second spaced apart floating gates.

Semiconductor memory devices and methods for fabricating the same

A method and system of controlling a process from run-to-run for semiconductor manufacturing. The method of control utilizes a process model to establish a relationship between process control input data and process control output data. The method of control involves minimizing the difference between target process control output data and process control output data predicted by applying the process model to the new process control input data.

Method and system for run-to-run control

A method is provided for determining an etch endpoint. The method includes collecting intensity data representative of optical emission spectral wavelengths during a plasma etch process. The method further includes analyzing at least a portion of the collected intensity data into at most first and second Principal Components with respective Loadings and corresponding Scores. The method also includes determining the etch endpoint using the respective Loadings and corresponding Scores of the second Principal Component as an indicator for the etch endpoint using real-time Principal Components Analysis applied to optical emission spectral data from a previous portion of the plasma etch process.

Determining endpoint in etching processes using real-time principal components analysis of optical emission spectra

A method is provided for determining an etch endpoint. The method includes collecting intensity data representative of optical emission spectral wavelengths during a plasma etch process. The method further includes analyzing at least a portion of the collected intensity data into at most first and second Principal Components with respective Loadings and corresponding Scores. The method also includes determining the etch endpoint using the respective Loadings and corresponding Scores of the second Principal Component as an indicator for the etch endpoint using Principal Components Analysis applied to archived optical emission spectral data.

Determining endpoint in etching processes using principal components analysis of optical emission spectra

A method is provided for determining an etch endpoint. The method includes collecting intensity data representative of optical emission spectral wavelengths during a plasma etch process. The method further includes analyzing at least a portion of the collected intensity data into at most first and second Principal Components with respective Loadings and corresponding Scores. The method also includes determining the etch endpoint using the respective Loadings and corresponding Scores of the second Principal Component as an indicator for the etch endpoint using thresholding applied to the respective Loadings of the second Principal Component.

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Austin, TX, United States of America

Joseph William Wiseman