International Business Machines Corporation

Bae Systems Information and Electronic Systems Integration Inc.

Joseph W Yoder

Jeanne P Bickford

Bin Li

John Stanley Bialas, Jr

Nadim F Haddad

Johnny James LeBlanc

Edward Kelley Evans

Raymond J Rosner

Andrew S Wienick

Thomas M Storey

Richard J Daniels

Joseph A Hoffman

Abbas Kazemzader

Dave C Lawson

Sean Horner

Henry C Baron

A method and system for predicting manufacturing yield for a proposed integrated circuit The method includes: in the order recited: (a) providing a multiplicity of different integrated circuit library elements in a design database, each library element linked to a corresponding normalization factor in the design database; (b) selecting library elements from the design database to include in a proposed design for the integrated circuit; (c) generating an equivalent circuit count of the proposed design based on the normalization factors and a count of each different library element included in the proposed design; and (d) calculating a predicted manufacturing yield based on the equivalent circuit count, a predicted density of manufacturing defects and an area of the proposed integrated circuit chip.

Method for modeling integrated circuit yield

A scannable flip flop for space-based LSSD testable integrated circuits. A scannable register can be formed from the scannable flip flops. The scannable flip flops can be radiation hardened. Each scannable flip flop can include a 2:1 input multiplexer, a first latch and a second latch. The input multiplexer is coupled to the first latch by a pair of pass gates. The pass gates are gated by a first clock input signal. A second pass gate pair couples the first latch to the second latch. A second clock input signal gates the second pass gate pair. The first and second clock input signals are non-overlapping. The latch can be employed in edge triggered logic ECAD tools for designing IC. The resulting IC logic can be tested using LSSD test testing techniques and patterns.

Method and apparatus for a scannable hybrid flip flop

A clock splitter circuit for providing a single event upset (SEU) tolerant clock signal to latches in a space-based environment. The clock splitter circuit can include one or more event offset circuit delay circuits. The event offset delay receives a clock signal and generates a delayed clock signal. The event offset delay circuit can generate an inverted clock signal, a delayed inverted clock signal and a pair of intermediate clock signals. The delayed clock signal and inverted delayed clock signal can be delayed by the known duration of single event effects (SEE). The delayed and undelayed clock signals can be passed to an event blocking filter which can block any disturbance in the delayed and/or undelayed clock signals. A synchronizer can synchronize outputs of the event blocking filter prior to or coincident with being passed to corresponding inverting clock drivers. The synchronizers can also insure that the synchronized blocking filter outputs can not be low simultaneously. Intermediate clocks can also be provided corresponding to the inverting clock drivers. Outputs of the inverting clock driver can be a pair of SEU tolerant non-overlapping clock phase signals for driving one or more latches.

Method and apparatus for a single upset (SEU) tolerant clock splitter

A single event effect immune oscillator circuit is disclosed. The single event upset immune oscillator circuit includes an odd number of logic circuit blocks connecting in series to provide a continuous pulse signal at an output of the oscillator circuit. Each logic circuit block has a first input, a second input, and an output. For a series of logic circuit blocks i, where i&equals;1 to n (n is an odd number), the output of a logic circuit block i is connected to a first input of a logic circuit block i&plus;1. The output of the logic circuit block i is also connected to a first input of a logic circuit block i&plus;x, wherein x is an odd number greater than one and less than or equal to n.

Single event upset immune oscillator circuit

A circuit for filtering single event effect (SEE) induced glitches is disclosed. The circuit for filtering SEE induced glitches comprises an SEE immune latch circuit and a delay element. The SEE immune latch circuit includes a first input, a second input, and an output. The SEE immune latch changes from one state to another state only upon having incoming input signals of identical polarity being applied contemporaneously at both the first input and the second input. The first input of the SEE immune latch circuit is directly connected to a signal input, and the second input of the SEE immune latch circuit is connected to the signal input via the delay element. The delay element provides a signal delay time equal to or greater than a pulse width of an SEE induced glitch but less than a pre-determined pulse width of an incoming signal at the signal input under normal operation. By connecting the delay element between the signal input and the second input of the SEE immune latch circuit, a temporal separation greater that the duration of an SEE induced glitch can be achieved on the data being drive into the first and the second inputs of the SEE immune latch circuit. As a result, SEE induced glitches will not be written into the SEE immune latch circuit.

Circuit for filtering single event effect (see) induced glitches

The improved register file includes an array of storage cells arranged in columns and rows, each column having a pair of bit lines for writing into the cell. Each storage cell includes a flip-flop cell having a first storage node connected to a respective read line which is unique for that cell. A read address latch has an enabling input connected to the master clock signal which is the same master clock signal for the LSSD logic on the integrated circuit chip. The read address latch applies its decoded output to a multiplexer which selects those read lines coming from one of the rows of storage cells in the array, and applies those selected read lines to an output storage cell array. The output storage cell array is enabled by a slave clock signal which is the same slave clock signal employed in the LSSD logic on the same integrated circuit chip. The output storage cell array stores the data from the selected read lines out of the multiplexer. The multiplexer propagates the data signals output from the read lines and performs the selection during the delay period between the master clock signal and the slave clock signal. Thus, the circuit makes use of the dead time between the master clock signal and the slave clock signal which was heretofore wasted, in performing the selection of the read lines for latching in the output storage cell array. The feature of connecting separate read lines to each respective storage cell in the array allows the independent accessing of different register rows in the register file for reading and writing, during the same logic cycle defined by the interval for the occurrence of both the master and the slave clock pulses.

High density, high performance register file having improved clocking

A CMOS flip-flop circuit is disclosed which enables a single side pull-down operation for inputting test signals during a test mode and alternately a dual side push-pull operation for inputting data signals during the normal use of the circuit. A pair of inverter circuits selectively feed complementary data signals to opposite sides of a bistable circuit so that the circuit operates in the push-pull manner thereby decreasing the switching time of the flip-flop. A pair of transmission gates, which are coupled to outputs of the inverter circuits, electrically isolate any noise appearing at a data input from the bistable circuit. During a test mode of the flip-flop, a test signal is fed into one side of the bistable circuit and facilitates a single side pull-down operation of the flip-flop. Two such flip-flop circuits are concatenated in a push-pull cascaded connection to provide a shift register latch.

High speed CMOS latch with alternate data storage and test functions

A soft error protection circuit is disclosed for a storage cell, such as a latch having a first input/output node and a second input/output node which are respectively connected to a charging source, the first node being selectively charged at least during a write interval, to represent a stored, first binary logic state for the latch. The circuit includes an insulated gate, field effect capacitor having a diffusion electrode connected to the second node and having a gate electrode, for selectively loading the second node with an additional capacitance. An inverter circuit has an input connected to the second node and an output connected to the gate electrode of the capacitor, for applying a capacitance enhancing bias to the gate electrode in at least a read interval following the write interval, when the first binary logic state has been stored in the latch, to apply the additional capacitance to the second node. The charging source supplies charge to both the first node and the second node at least following a soft error event which has caused the first node to become at least partially discharged during the read interval. In accordance with the invention, the additional capacitance applied to the second node prevents the second node from recharging as fast as the first node following the soft error event, by sinking a portion of the charge supplied from the charging source to the second node. In this manner, the first node will resume its previously charged condition, thereby preserving the stored logic state.

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Fairfax Station, VA, United States of America

Joseph W Yoder