Microchip Technology Inc.

Joseph W Triece

Rodney J Drake

Rodney J Pesavento

Randy L Yach

Igor Wojewoda

Sumit K Mitra

Gregg Lahti

Steven Dawson

Joshua M Conner

Edward Brian Boles

Darrel Johansen

Michael I Catherwood

Brian E Boles

Jennifer Yuan Chiao

Michael S Pyska

Tim Wilson

James H Grosbach

Steve Allen

Bryan Kris

Joseph Alan Thomsen

D C Sessions

Pieter Schieke

Cristian P Masgras

J Clark Rogers

Laurentiu Birsan

Mitchel Obolsky

Mei-Ling Chen

Tyler Nye Boddie

Robert Sean Justice

Manish Patel

Clark J Rogers

James Grosbach

Rodney Jay Drake

Darrel Ray Johansen

Tim L Wilson

Steven G Dawson

Johansen Darrel

Michael Pyska

A direct memory access (DMA) controller, includes circuitry configured to load a DMA transfer descriptor configured to define which memory elements within a contiguous block of n memory elements are to be included in a given DMA transfer. The circuitry is further configured to, based on the DMA transfer descriptor, determine whether each memory element within the contiguous block of n memory elements is to be included in the given DMA transfer, including a determination that two or more non-contiguous sub-blocks of memory elements within the contiguous block of n memory elements are to be transferred. The circuitry is further configured to, based on the determination of whether each memory element within the contiguous block of n memory elements is to be included in the given DMA transfer, perform the DMA transfer of memory elements determined to be included within the given DMA transfer.

DMA-scatter and gather operations for non-contiguous memory

A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

Direct memory access controller

A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.

Configurable cache for a microprocessor

A microcontroller or integrated system has a bus, a plurality of peripheral devices each one coupled with the bus, a non-volatile memory, and a state machine coupled with the non-volatile memory and being operable to initialize the peripheral devices by reading initialization information from the non-volatile memory and writing it to the peripheral devices.

Dynamic state configuration restore

A processor has a central processing unit (CPU), a first CPU register set, a second CPU register set, a multiplexer logic for either coupling the first or the second CPU register set with the CPU, and control logic for controlling the multiplexer logic to switch from the first CPU register set to the second CPU register set upon receipt of at least one of a plurality of interrupt signals, wherein the at least one of a plurality of interrupt signals must meet a condition that is programmable within the control logic.

Processor with assignable general purpose register set

An integrated circuit device has a digital device operating at an internal core voltage; a linear voltage regulator; and an internal switched mode voltage regulator controlled by the digital device and receiving an external supply voltage being higher than the internal core voltage through at least first and second external pins and generating the internal core voltage, wherein the internal switched mode voltage regulator is coupled with at least one external component through at least one further external pin of the plurality of external pins.

Integrated circuit device with two voltage regulators

A controller area network (CAN) controller unit has a message assembly buffer receiving a serial bitstream, a buffer memory coupled in parallel with said message assembly buffer, a CAN control unit coupled with the message assembly and the buffer memory, and at least one control register. The at least one control register can be programmed to cause the CAN control unit to store a message received in the message assembly register in at least a first and second mode, wherein in the first mode, control information and data payload of the received CAN message are stored in the buffer memory and in the second mode only the data payload of the CAN message is stored in the buffer memory.

Method for CAN concatenating CAN data payloads

A microcontroller has a random access memory, and a Controller Area Network (CAN) controller with a control unit receiving an assembled CAN message. The control unit generates a buffer descriptor table entry using the assembled CAN message and stores the buffer descriptor table entry in the random access memory, and the buffer descriptor table entry has at least a message identifier and load data from the CAN message and information of a following buffer descriptor table entry.

Microcontroller with CAN module

A system has a central processing unit (CPU) operable to operate in a sleep or low power mode and in an active mode, a plurality of system components operable to operate in a sleep or low power mode and in an active mode, and a direct memory access (DMA) controller operating independently from the CPU and operable to operate in a sleep or low power mode and in an active mode, wherein the DMA controller is further operable to transfer data from and to a memory or peripheral device, wherein when the system is in a sleep or low power mode, only the DMA controller and any system component which is necessary to perform a DMA transaction are switched into active mode.

A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory wherein the cache memory has a plurality of cache lines, each cache line having a storage area for storing instructions to be issued sequentially and associated control bits, wherein at least one cache line of the plurality of cache lines has at least one branch trail control bit which when set provides for an automatic locking function of the cache line in case a predefined branch instruction has been issued.

A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions to be issued sequentially and at least one control bit field, wherein the control bit field is coupled with the address tag bit field to mask a predefined number of bits in the address tag bit field.

An interrupt controller has an interrupt register unit receiving a plurality of interrupt source signals, an interrupt detector coupled to the interrupt register unit, a counter unit coupled to the interrupt detector, wherein on the first occurrence of an interrupt source signal the counter unit defines a time window during which the interrupt register stores further interrupt source signals, and an interrupt request unit coupled to the counter unit for generating an interrupt request signal.

Interrupt controller handling interrupts with and without coalescing

A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.

Enabling special modes within a digital device

Fast access of a memory having a stack uses an address bit, a stack pointer, and fast access random access memory ('RAM'). When a first address mode is used in conjunction with the address bit and the stack pointer, the location of the access RAM can be shifted in order to achieve an index of a literal offset address mode.

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Phoenix, AZ, United States of America

Joseph W Triece