Northrop Grumman Systems Corporation

Joseph Terence Smith

Harvey C Nathanson

Patrick Bruckner Shea

Dennis Allen Adams

Robert Samuel Howell

Nathan Bluzer

Robert Miles Young

Marvin H White

Michael Rennie

James Halvis

Christopher F Kirby

Thomas J Knight

Garrett A Storaska

Paul A Tittel

Archer S Mitchell

Bron R Frias

Robert R Shiskowski

A photovoltaic semiconductor solar cell with a backside semiconductor-oxide-nitride-oxide nonvolatile charge storage structure (referred to as a 'PHONOS solar cell') is disclosed. The PHONOS solar cell includes a semiconductor surface region, a semiconductor bulk region, and a backside structure that includes the SONO nonvolatile charge storage structure and a backside contact. The backside SONO nonvolatile charge storage structure greatly improves solar cell efficiency gains by eliminating 'backside' losses, i.e., losses due to the recombination of photo-generated minority charge carriers created by the incident sunlight. The PHONOS solar cell is a highly efficient, ultra-thin, semiconductor solar cell that can be manufactured at low cost.

Photovoltaic silicon solar cells

An embodiment of a method is disclosed to integrate silicon oxide nitride oxide silicon (SONOS) non-volatile memory (NVM) into a standard sub-90 nm complementary metal oxide semiconductor (CMOS) semiconductor foundry process flow. An embodiment of the method adds a few additional steps to a standard CMOS foundry process flow and makes minor changes to the rest of the baseline CMOS foundry process flow to form a new process module that includes both CMOS devices and an embedded SONOS NVM. An embodiment of the method utilizes new material sets (which are not utilized at larger nodes) that enhance NVM performance by improving charge tunneling behavior and reducing leakage currents. Furthermore, an embodiment of the method integrates CMOS with SONOS NVM at ever-shrinking dimensions while enhancing the NVM performance, without performing extra, costly processing steps.

Method for integrating SONOS non-volatile memory into a sub-90 nm standard CMOS foundry process flow

An Indium Tin Oxide (ITO) gate charge coupled device (CCD) is provided. The CCD device comprises a CCD structure having a substrate layer, an oxide layer over the substrate layer, a nitride layer over the oxide layer and a plurality of parallel ITO gates extending over the nitride layer. The CCD device further comprises a plurality of substantially similarly sized channel stop regions in the substrate layer that extend transversely relative to the ITO gates, such that a given pair of channel stop regions defining a pixel column of the CCD structure. The CCD device also comprises a plurality of vent openings that extend through the nitride layer along the plurality of substantially similarly sized channel stop regions to allow for penetration of hydrogen to at least one of the oxide layer and the substrate layer.

Indium tin oxide gate charge coupled device

An embodiment of a method is disclosed to integrate silicon oxide nitride oxide silicon (SONOS) non-volatile memory (NVM) into a conventional complementary metal oxide semiconductor (CMOS) semiconductor foundry process flow. An embodiment of the method only adds a few additional steps to a standard CMOS foundry process flow and makes minor changes to the rest of the baseline CMOS foundry process flow to form a new process module that includes both CMOS devices and an embedded SONOS NVM.

Method for integrating SONOS non-volatile memory into a standard CMOS foundry process flow

A high-efficiency lateral multi-junction solar cell (C) includes ultra-low profile planar spectral band splitting micro-optics having a shortpass filter () reflecting desired frequencies of light () to a reflective mirror () combined with spectrally optimized photovoltaic (solar) cells.

Lateral ultra-high efficiency solar cell

One example discloses a heat transfer device that can comprise a semiconductor material having a first region and a second region. The first region and the second region are doped to propel a charged carrier from the first region to the second region. The heat transfer device can also comprise an array of pointed tips thermoelectrically communicating with the second region. A heat sink faces the array, and a vacuum tunneling region is formed between the pointed tips and the heat sink. The heat transfer device further can further comprise a power source for biasing the heat sink with respect to the first region. The first region defines an N-type semiconductor material and the second region defines a P-type semiconductor material.

Heat transfer device

A device includes a coiling layer, a circuit device layer and active microelectronic circuitry fabricated on the circuit device layer. The coiling layer is formed onto a surface of and coupled to the circuit device layer. The coiling layer having intrinsic stresses which cause coiling of the coiling layer and the circuit device layer including the microelectronic circuitry as the circuit device layer is released from an underlying substrate. A coiled circuit device is formed.

Coiled circuit device with active circuitry and methods for making the same

A coiled camera includes a coiling layer, a circuit device layer, active microelectronic circuitry fabricated on the circuit device layer, a semiconductor imaging device electronically coupled to the active microelectronic circuitry and a lens coupled to the semiconductor imaging device.

Growing community of inventors

Columbia, MD, United States of America

Joseph Terence Smith