Motorola Corporation

Joseph T Marino, Jr

Ronald S Core

Bruce Alan Fette

Ronald V Chandos

Paul Aerick Lambert

Chris B Curtis

Ernest W Borgoyne, Jr

Ronald J Young

In a digital channel of a digital wireless communication system including at least one mobile station, at least one base transceiver station in communication with the mobile station, a transcoder configured to provide a signal conversion between vocoder frames and pulse code modulation, and a mobile switching center for interconnecting the digital wireless communication system to a public switched telephone network, a method and apparatus for determining a fault in the digital channel is disclosed. The method includes generating a first set of vocoder input parameters from a speech input signal, and generating a second set of vocoder input parameters from an output signal substantially equivalent to the speech input signal as it is received at a mobile station via the digital channel. The method further includes calculating a metric based on the first and the second set of vocoder input parameters, and subsequently determining a fault in the digital channel using the metric.

Method and apparatus for testing digital channels in a wireless communication system

A computer network (20) including secure nodes (26) and unsecured nodes (28). The secure nodes (26) may communicate private data without compromising security provisions. The secure nodes (26) include a security kernel (36) that implements communication security provisions and a trusted operating system (40) that imposes computer data security provisions. A trusted interface (44) is used to transfer data between the trusted operating system (40) and the security kernel (36). In addition, this interface (44) insures that computer security attributes are compatible with communication security attributes. If incompatibilities are discovered, requested communications are thwarted and audit records for the security linkage violations are recorded.

Operational methods for a secure node in a computer network

A security kernel of a secure processing system for providing security management, key management and kernel security functions. The secure processing system includes two parallel subsystems, a red subsystem and a black subsystem. The red subsystem may communicate only with the kernel since this system transfers plain text data. The black subsystem may communicate with the red subsystem and also other processing systems for the transmission of cypher text data. The security kernel is a single standard interface for tasks associated with the red and black subsystems for communicating in a secure manner with one another and with other processing systems. Various security services are provided to red and black subsystem applications by a single security kernel.

Uniform interface for cryptographic services

A secure processor arrangement for a communications secure kernel of a secure processor system. This processor arrangement provides protection of plain text data and suitable isolation of data necessary to support single processor architecture. A red memory subsystem stores plain text data and a black memory subsystem stores cypher text data. In order to prevent mishandling of plain text data, the single processor is allowed to directly read and to write red memory, but the single processor is only permitted to directly read from the black memory.

Secure cryptographic processor arrangement

The present invention consists of a hardware simulator with bus evaluator logic for use in simulating and fault grading of very large scale digital circuits containing buses. In this invention the status of a bus is continously upgraded each time a primitive is evaluated that has an output coupled to the bus. As bus driver primitives are evaluated, the state of the bus is determined on the fly and stored in an accumulator register, called the bus register. Evaluation of the bus continues using the data stored in the bus register and the state of each driver until all drivers have been evaluated. After the last bus driver is evaluated the state of the bus is known and the bus primitive is assigned the value, or state, stored in the bus register hardware and is passed to all receivers on the bus.

Wired 'OR' bus evaluator for logic simulation

A hardware simulator for simulating digital structures includes a general purpose computer and an improved simulator processor. The improved processor handles an advanced primitive having four inputs and one output and which is capable of representing a memory cell or similar structure. The architecture of the processor provides highly efficient compilation of the input states of a primitive and the primitive evaluator and resolver logic provide the output state in a minimum number of clock cycles. The simulator is a single, low cost unit capable of simulating 64K cell structures with a speed comparable to prior art simulators.

Processor for simulating digital structures

A DES (Data Encryption Standard) system utilizing an input register, control logic and output register to provide for a selection from a multiplicity of operable modes on a single chip or family of chips.

Flexible mode DES system

A system for providing on-line parity checking in data encryption/decryption systems such as DES and which is especially useful where multiple stage shifting is accomplished on a single clock input to the algorithm shift register of such a system. The parity system provides for simultaneous parity checks on a plurality of bytes where the bits of each byte are distributed through the algorithm shift register in a pseudorandom pattern.

Growing community of inventors

Fountain Hills, AZ, United States of America

Joseph T Marino, Jr