Apple Inc.

Joseph T DiBene, Ii

Inder M Sodhi

Shawn Searles

Gerard Richard Williams

Jun Zhai

Keith Alan Cox

Vidhya Ramachandran

Kunzhong Hu

Chonghua Zhong

Mengzhi Pang

Jafar Savoj

Sotirios Zogopoulos

David P Cappabianca

Brad W Simeral

Cyril De La Cropte De Chanterac

Sanjay Pant

Yizhang Yang

David A Hartley

Paul McCloskey

Le Wang

Sean Cian O'Mathuna

Rashed Mahameed

Zoran Pavlovic

Santosh Kulkarni

William Lawton

Graeme Maxwell

Joseph O'Brien

Hugh Charles Smiddy

In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g., with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

Systems and methods for coherent power management

Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

Structure and method for fabricating a computing system with an integrated voltage regulator module

An inductor is disclosed, including a first wire, a non-conductive material, and a shell. The non-conductive material may cover the first wire, with a portion of each end of the first wire uncovered. The shell may include a top portion and a bottom portion and include at least one magnetized layer and at least one gap between the first portion and the second portion. The shell may also surround a portion of the non-conductive material.

Coupled inductor structures utilizing magnetic films

In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

In an embodiment, a system may support a 'coast mode' in which the power management unit (PMU) that supplies the supply voltage to an integrated circuit is disabled temporarily for certain modes of the integrated circuit. The integrated circuit may continue to operate, consuming the energy stored in capacitance in and/or around the integrated circuit. When coast mode is initiated, a time interval for coasting may be determined. When the time interval expires, the PMU may re-enable the power supply voltage.

Reduced power operation using stored capacitor energy

An embodiment of a system is disclosed, including an inductor, a voltage regulating circuit, a load, and a current detecting circuit. The inductor includes a first wire, a second wire, and a third wire. The third wire is between, and may be inductively coupled to, the first wire and the second wire. The voltage regulating circuit is coupled to a first end of the first wire and a first end of the second wire. The voltage regulating circuit is configured to generate a first current through the first wire and a second current through the second wire. The load is coupled to a second end of the first wire and a second end of the second wire. The current detecting circuit, coupled to ends of the third wire, is configured to generate an output signal based on a third current through the third wire.

Tertiary winding for coupled inductor structures

In various embodiments, a voltage collection bootstrap circuit includes a capacitor, an inductor, an oscillator, a bias circuit, and a switch. A current may be induced in the inductor, the oscillator, or both. The inductor, the oscillator, or both may store energy in the capacitor. The inductor, capacitor, and oscillator may supply energy to the bias circuit. The bias circuit may output a difference between a reference voltage and a voltage corresponding to the energy received from at least one of the inductor, capacitor, and oscillator. Based on the output of the bias circuit, a switch may connect the voltage collection circuit to an output of at least one of the inductor, capacitor, and oscillator. Accordingly, energy may be provided to the voltage collection circuit using one or more induced currents.

Voltage collection bootstrap circuit

In one embodiment, an integrated circuit includes a power management architecture in which one or more pipelines are actively powered and clocked when data is provided for processing, but which are clock gated and in retention when there is no data to be processed. When data is provided to the pipeline, supply voltage may be actively provided to initial stages of the pipeline and the clocks may be ungated when the voltage is stable enough for operation. Subsequent stages of the pipeline may be sequentially provided power and clocks as the data progresses through the pipeline. Initial stages may be clock gated and power may be deactivated when additional data is not provided for processing. Accordingly, when the pipeline is viewed as a whole, power may be seen as rolling forward ahead of the data processing, and power may be inhibited in a similar rolling fashion.

Power management architecture

An apparatus for determining an average current through an inductor of a regulator circuit is disclosed. A counter unit may be configured to receive a control signal, which includes a plurality of pulses, from a Power Management Unit (PMU), and determine a number of pulses received during a predetermined period of time. A pulse sampler unit may determine a duration of a given pulse of the plurality of pulses. Circuitry may be configured to determine the average current through the inductor during the predetermined period of time dependent upon the number of pulses received during the predetermined period of time and the duration of the given pulse.

Current and input voltage sense circuit for indirectly measuring regulator current

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Santa Cruz, CA, United States of America

Joseph T DiBene, Ii