Motorola Corporation

Joseph Shor

Yachin Afek

Mark Yosefin

Vladimir Koifman

Natan Baron

Eytan Engel

Dan M Bruck

A circuit arrangement (100) is coupled to a resistor (150) having at least two portions (110, 120). The arrangement (100) provides a substantially linear performance of the resistor (150). The arrangement (100) comprises a differential difference amplifier (160) (with input stages (170, 180) and output stage (190)) and a feedback unit (130). The input stages (170, 180) modify first (161) and second (162) measurement signals (e.g., (V.sub.B -V.sub.A) and (V.sub.A -GND), respectively) from the resistor portions (110, 120) to intermediate signals (OPH, OMH, OPL, OML). The output stage (190) differentially amplifies sums (at nodes 191, 192) of the intermediate signals and provides a control signal (CONTROL) which corresponds to a magnitude difference between the first and second measurement signals. The feedback unit (130) receives the control signal and supplies a corrective current (I) to the resistor (150) to offset non-linearity.

Circuit arrangement to compensate non-linearities in a resistor, and

In a circuit (10), a first N-FET (N1) and a second N-FET (N2) are coupled serially between a node (15) and ground (93). The circuit (10) accommodates a first excursion (85) of a first signal (IN) at the gates of the first N-FET (N1) which is higher than the maximum allowable drain-source voltage for N-FETs. The voltage of a second signal (OUT) between the node (15) and ground (93) is distributed across the first and the second N-FETs (N1, N2). The gate voltage of the second N-FET (N2) is not constant, but controlled by a control circuit (20) receiving signals the first signal (IN) and, optionally, the second signal (OUT). With the variation of the gate voltage for the second N-FET (N2), the size of both transistors (N1, N2) can be reduced and the fall time (T.sub.F) of the second signal (OUT) can be reduced.

Circuit with hot-electron protection and method

An I/O circuit whose output receives a voltage V.sub.PAD which is temporarily higher than a critical voltage V.sub.DS MAX &gt;V.sub.DS 1 across drain and source of a conducting first N-FET (110, N1) acting as a pull-down device. The first N-FET is protected against hotelectron induced degradation by a serially coupled second N-FET (130, N3). A variable drain-source voltage V.sub.DS 3 is added to V.sub.DS 1. A comparator (150) compares the received voltage V.sub.PAD to a supply voltage V.sub.CC and pulls a gate (G) of the second N-FET (N3) to V.sub.PAD or to V.sub.CC. The conductivity of the second N-FET (N3) is thereby changed so that VPAD is distributed among V.sub.DS 1 and V.sub.DS 2. The comparator (150) conveniently comprises two P-FETs (P1, P2, 160, 170).

Circuit with hot electron protection and method

The electronic circuit (100) of the invention receives first signals DATA (170) having logical '1' at high (VCCH) or low (VCCL) levels and logical '0' at reference level (ZERO) and generates second signals OUT (186) between high level (VCCH) and reference level (ZERO) without changing the information. The circuit comprises a first switch (161) and a second switch (161) serially coupled together to a common output node (103). The first switch (162) is controlled by a control signal (CTRL) derived from DATA, OUT, or optionally from a clock signal CLK. The first switch (161) is switched off before the second switch (162) is switched off. Contention (conducting at the same time) is thereby avoided and the first switch (161) and the second switch (162) can be implemented by substantially equal-sized components.

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Raanana, Israel

Joseph Shor