Intel Corporation

Saifun Semiconductors Ltd.

Birad-research & Development Company Ltd.

Bar-ilan University

Birad—research & Development Corapany Ltd.

Joseph Shor

Eduardo Maayan

Eyal Fayneh

Yoram Betser

Yair Sofer

Noam Familia

Kosta Luria

Yan Polansky

Fabrice Paillet

Michael Zelikson

Alexander Lyakhov

George L Geannopoulos

Yoav Weizman

Yitzhak Schifmann

Avigdor Saksonov

Vivek K De

James W Tschanz

Alexander Fish

Oleg Dadashev

Victor Zia

Anatoli Mordakhay

Roi Levi

Shai Eisen

Avri Harush

Hong Yun Tan

Yitzhak Elhanan Schifmann

Adam Zaidel

Avi Miller

Netanel Shavit

Edison Ramiro Taco Lasso

Inbal Stanger

Lan D Vu

Ori Bass

Liron Lisha

Natan Vinshtok-Melnik

Dadashev Oleg

Yitzhak Shifman

Luria Kosta

A technique to mitigate timing errors induced by power supply droops includes an inverter-based droop detector as well as Dual Mode Logic (DML) to achieve a droop-resist ant timing response. The droop detector is based on capacitor ratios and is thus less sensitive to Process/Voltage/Temperature (PVT) and to random offset than the prior art. The DML can alter its power/performance ratio based on the droop level input it receives from the detector, such that the critical timings are preserved.

Method for mitigation of droop timing errors including a droop detector and dual mode logic

A method for creating a physical unclonable function (PUF) bit for use with transistor circuitry includes performing a tilt test on a PUF cell of a transistor circuitry, comprising tilting the PUF cell at least once, and comparing a mismatch of a response of the PUF cell to a tilt threshold. A magnitude of the mismatch is determined. A mismatch magnitude below the tilt threshold is considered a first logic value' and a mismatch magnitude above the tilt threshold is considered a second logic value. The mismatch magnitude of the PUF cell is random. The absolute value of the mismatch magnitude is used as an entropy source to produce at least one PUF bit called a mirror PUF bit.

Method to utilize mismatch size to produce additional stable bit in tilting PUF

A sensor circuit includes a bandgap reference circuit (BGREF) that produces two outputs, a temperature dependent output and a reference voltage, which does not change with temperature. The temperature dependent output includes a PTAT (proportional to absolute temperature, rising with increased temperature) portion and a CTAT (complementary to absolute temperature, falling with increased temperature) portion. Circuitry is provided that calculates the reference voltage by adding the PTAT portion and a divided version of the CTAT portion in which the CTAT portion has been divided by a divisor.

Miniaturized digital temperature sensor

A process monitor circuitry is described that can measure the electron mobility (&#x3bc;), oxide capacitance (C) and threshold voltage (V) of an integrated circuit.

Process monitor circuitry with measurement capability

A method for detecting unreliable bits in transistor circuitry includes applying a controllable physical parameter to a transistor circuitry, thereby causing a variation in a digital code of a cryptologic element in the transistor circuitry, the variation being a tilt or bias in a positive or negative direction. An amount of variation in the digital code of the cryptologic element is determined. Unreliable bits in the transistor circuitry are defined as those bits for which the variation is in a range defined as unreliable.

Detecting unreliable bits in transistor circuitry

A sensor circuit includes at least one ring oscillator having a supply port supplied by at least one current source and a reference frequency. A comparator compares a frequency output of the at least one ring oscillator with the reference frequency to yield a measurement, such as a temperature measurement.

Ring oscillator temperature sensor

A thermal sensor includes a first resistor and a first capacitor. The first resistor is a thermistor. A first current source is coupled to the first resistor and the first capacitor. The first current source alternately charges the first resistor and the first capacitor each to a reference voltage, V. An output of the thermal sensor is a function of a resistance-capacitance (RC) time constant of the first resistor and the first capacitor.

Miniaturized thermistor based thermal sensor

Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.

Low dropout voltage regulator integrated with digital power gate driver

A method for detecting unreliable bits in transistor circuitry includes adjusting a value of a variable capacitor coupled to a physical unclonable function (PUF) cell of a transistor circuit. The adjusting includes tilting the PUF cell to either a zero or one state: if the PUF cell changes its state during the tilting it is deemed unstable, and if the PUF cell does not change its state during the tilting it is deemed stable.

Two bit/cell SRAM PUF with enhanced reliability

A physical unclonable function (PUF) array includes a plurality of PUF transistor cells each of which includes at least one inverter. An input and an output of the at least one inverter are shorted to a first reference node. There is adjustment circuitry for adjusting a reference voltage of the first reference node, and measurement circuitry for measuring a trip point of the at least one inverter. If the trip point is close to the reference voltage then bits of the at least one inverter are defined as unstable.

Physical unclonable functions related to inverter trip points

A bandgap reference (BGREF) circuit includes at least one switch capacitor impedance element including a capacitor coupled with switches that receive a reference frequency. The at least one switch capacitor element is coupled with at least one diode. The BGREF circuit is operative to create a voltage reference.

Switch capacitor in bandgap voltage reference (BGREF)

A disable module may be coupled to an analog circuit of an electronic circuit. The disable module may detect an input voltage that is supplied to the analog circuit, and may disable (such as by powering off) the analog circuit if the input voltage is below a reference value. The reference value may be set at a voltage level at or below a maximum voltage that may be present across a transistor in the analog circuit. Accordingly, the analog circuit may be disabled without damage to the transistors of the analog circuit. The disable module may detect whether the input voltage is below the reference value level by comparing the input voltage to a reference voltage. The electronic circuit may include a voltage regulator, and the voltage regulator may include the analog circuit.

Apparatus and method for selectively disabling one or more analog circuits of a processor during a low power state of the processor

Described is an apparatus which comprises: a bandgap core to provide a control signal; and an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at an output node.

Bandgap reference circuit with low output impedance stage and power-on detector

Some embodiments include apparatuses and methods having a digitally controlled oscillator (DCO) in a digital phase-locked loop (PLL) and a control loop. The DCO can generate an output signal having a frequency based on a value of a digital information. The control loop can adjust a value of a supply voltage of the DCO based on the value the digital information. Additional apparatuses and methods are described.

Digital phase-locked loop supply voltage control

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Tel Mond, Israel

Joseph Shor