Marvell International Limited

Joseph Sheredy

Lau Nguyen

Sehat Sutardja

Saeed Azimi

Son Hong Ho

Alan Armstrong

Justin Heindel

Kevin Tonthat

Hai Van

Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write-erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.

Method and apparatus for selecting a memory block for writing data, based on a predicted frequency of updating the data

Method and apparatus for storing data in a flash memory including single level memory cells and multi level memory cells

Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write&#x2014;erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write&#x2014;erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.

Mixed multi-level cell and single level cell storage device

An apparatus and method are disclosed for correcting errors in data obtained from read operations on a storage medium. Errors that occur in a minority of read operations for the data are corrected by a voting technique. The data may then be processed with error correcting code to correct errors that occur in a majority of read operations.

Soft error correction for a data storage mechanism

A memory storage system includes a line cache including a plurality of pages. A first central processing unit (CPU) accesses data stored in the pages of the line cache. A first memory device stores data that is loaded into the line cache when a miss occurs. After an initial miss, the line cache prevents additional misses as long as the first CPU is addressing sequential memory locations of the first memory device. When the miss occurs, n pages of the line cache are loaded with data from sequential locations in the first memory device, wherein n is greater than one. When the CPU requests data from an mpage of the n pages in the line cache, wherein m is greater than one and less than or equal to n, the line cache loads p additional pages with data from sequential locations in the first memory device.

Line cache controller with lookahead

A data storage device architecture includes a HDA printed circuit board (PCB) including a spindle motor driver, a read/write arm driver, a read channel driver, and a first input/output (I/O) interface that are arranged on the HDA PCB. An application PCB includes at least one of an application specific integrated circuit and a processor that performs application and hard drive control related processing. A buffer stores application and hard drive control related data. A hard drive controller (HDC), a mapping driver, and a second I/O interface are arranged on the application PCB. The second I/O interface communicates with the first I/O interface. The mapping driver is capable of at least one of mapping logical addresses to physical addresses and monitoring a location of a read/write head.

Architecture for a data storage device

Apparatus for testing a system on a chip (SOC) comprises a first SOC including a first hard disk controller and a first read channel. A second SOC comprises a second hard disk controller and a second read channel. An arbitrary waveform generator (AWG) generates a timing signal. An adder is provided in communication with the arbitrary waveform generator. The first SOC differentiates the timing signal received from the arbitrary waveform generator and generates a write signal in synchronization with the timing signal. The adder adds the write signal from the first SOC and the timing signal to output a combined signal having a timing signal component and a write signal component. The second SOC differentiates the timing signal component which simulates a servo signal and the write signal component simulates a signal being accessed by a read channel.

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San Jose, CA, United States of America

Joseph Sheredy