Intel Corporation

General Electric Company

Joseph Shappir

Ching-Yeu Wei

Joseph M Pimbley

Gennady Gildenblat

Ido Rahat

An improved density semiconductor device having a novel buried interconnect is described. The buried interconnect electrically connects electrical device regions on a semiconductor substrate such that other structures may directly overlie the buried interconnect but not be electrically connected to the electrically conductive portions of the interconnect. The interconnect is composed of a buried conductor and conductive segments. The conductive segments are electrically joined to the buried conductor so as to form an electrical pathway. First, a buried conductor is formed over an oxidized portion of a first field oxide. A layer of selective poly-epi silicon is then grown over the surface of the substrate. A nonconductive portion of selective poly-epi silicon is then formed over the buried conductor by oxidizing at least some of the selective poly-epi silicon layer. This nonconductive portion of the selective poly-epi silicon allows other structures to be formed over the buried conductor which are not in direct electrical contact with the buried interconnect. These other structures include elevated source/drain type structures, gates and silicidized or refractory metal local interconnects. These other structures may be selectively connected electrically to the conductive portions of the buried interconnect by the use of silicide segments or by the use of silicide segments connected electrically to titanium nitride pads. The conductive portion of the buried interconnect includes the buried conductor, and conductive segments which are formed by either silicon or silicide and which may include refractory metal pads. Silicide segments and titanium nitride pads are formed by depositing, annealing and etching a layer of refractory metal.

Buried interconnect structure for semiconductor devices

An improved density semiconductor device having a buried interconnect is described. The buried interconnect incorporates an elevated source/drain structure formed by selective poly-epi silicon growth and silicidized source/drain/gate interconnect segments. First, a buried conductor is formed over an oxidized portion of a first field oxide. A layer of selective poly-epi silicon is then grown over the surface of the substrate. At least some of the selective poly-epi silicon layer is then oxidized. A layer of refractory metal is then deposited, annealed, and etched to complete the buried interconnect.

Process for forming a novel buried interconnect structure for

A high-quality, highly reliable, composite dielectric layer for a semiconductor device. The composite dielectric layer is formed by nitriding a silicon surface, forming an oxide layer on the nitrided silicon surface, and then annealing the nitrided-silicon surface and the oxide in an oxygen ambient.

Composite dielectric for a semiconductor device and method of fabrication

Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a surface spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur. Additionally, a surface implant is performed to improve any gate control that may be lost as a result of the buried channel so as to mitigate any degradition of the current-voltage characteristics of the device.

Hybrid extended drain concept for reduced hot electron effect

Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a surface spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur. Additionally, a surface implant is performed to improve any gate control that may be lost as a result of the buried channel so as to mitigate any degradation of the current-voltage characteristics of the device.

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Jerusalem, Israel

Joseph Shappir