International Business Machines Corporation

Joseph S Newbury

Kevin K Chan

Judson Robert Holt

Cyril Cabral, Jr

Christian Lavoie

Dae-Gyu Park

Viorel C Ontalus

Abhishek Dube

Roy Arthur Carruthers

Ronnen Andrew Roy

Jinghong Li

Zhengmao Zhu

Paul Michael Kozlowski

Bruce Bennett Doris

Stephen W Bedell

Guy M Cohen

Vijay Narayanan

Arne Watson Ballantine

Isaac Lauer

Michael Patrick Chudzik

Kenneth Parker Rodbell

Zhen Zhang

Eduard Albert Cartier

Yu Zhu

Tze-Chiang Chen

Evgeni Petrovich Gousev

Vamsi Krishna Paruchuri

Barry P Linder

John Christopher Arnold

Matthew Warren Copel

Fenton Read McFeely

Alessandro Cesare Callegari

Gen Pei Lauer

Christopher Peter D'Emic

Patrick Ronald Varekamp

Harald F Okorn-Schmidt

Atul Champaklal Ajmera

Michael Abramovich Gribelyuk

Michelle Leigh Steen

Douglas Andrew Buchanan

James McKell Edwin Harper

Glenn A Biery

Young-hee Kim

Theodore Harold Zabel

Methods of etching a silicon substrate at a high rate using a chemical vapor etching process are provided. A silicon substrate may be etched by heating the silicon substrate in a process chamber and then flowing hydrochloric acid and a germanium-carrying compound into the process chamber. The substrate may be heated to at least 700&#xb0; C. The hydrochloric acid flow rate may be at least approximately 100 (standard cubic centimeters per minute) sccm. In some embodiments, the hydrochloric acid flow rate may be between approximately 10 slm and approximately 20 standard liters per minute (slm). The germanium-carrying compound flow rate may be at least approximately 50 sccm. In some embodiments, the germanium-carrying compound flow rate may be between approximately 100 sccm and approximately 500 sccm. The etching may extend fully through the silicon substrate.

High-rate chemical vapor etch of silicon substrates

Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.

Using fast anneal to form uniform Ni(Pt)Si(Ge) contacts on SiGe layer

Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.

Monolayer dopant embedded stressor for advanced CMOS

The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.

High performance CMOS circuits, and methods for fabricating same

Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes at least one monolayer of dopant located within the upper layer of each of the embedded stressor elements. The at least one monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

A method of forming a semiconductor substrate (and resultant structure), includes providing a semiconductor substrate to be silicided including a source and drain formed therein on respective sides of a gate, depositing a metal film over the gate, source and drain regions, reacting the metal film with Si at a first predetermined temperature, to form a metal-silicon alloy, etching the unreacted metal, depositing a silicon film over the source drain and gate regions, annealing the substrate at a second predetermined temperature, to form a metal-Si alloy, and selectively etching the unreacted Si.

Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby

A method for integrating a high-k material into CMOS processing schemes is provided. The method includes forming an interfacial oxide, oxynitride and/or nitride layer on a device region of a semiconductor substrate, said interfacial layer having a thickness of less than 10 &angst;; and (b) forming a high-k dielectric material on said interfacial oxide, oxynitride and/or, nitride layer, said high-k dielectric having a dielectric constant, k, of greater than 8.

Interfacial oxidation process for high-k gate dielectric process integration

Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial metal layer used in forming the silicide.

Method and structure for retarding high temperature agglomeration of silicides using alloys

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Irvington, NY, United States of America

Joseph S Newbury