Oracle International Corporation

Nxp Usa, Inc.

Joseph Rollin Wright

John E Watkins

Kumar Abhishek

Vivek Kumar Yadav

Erik Schlanger

Srikanth Jagannathan

John R Feehrer

Thomas Henry Luedeke

Anurag Jindal

Hemant Nautiyal

Nipun Mahajan

Eric Devolder

Rohan Poudel

Shruti Singla

Sanjaykumar Hansrajbhai Kakasaniya

Kushagra Khorwal

Vikram Joshi

Venkannababu Ambati

Mark Shelton Cinque

A method for handling faults in an integrated circuit system includes receiving fault interface signals from safety-critical logic and generating a fault request indicating a fault and a domain identifier based on the fault interface signals. The fault interface signals include a fault signal and a fault domain identifier signal. In an embodiment of the method, the fault interface signals include synchronous signals received from the safety-critical logic using a synchronous interface and the synchronous signals include a fault clock signal. In an embodiment of the method, generating the fault request includes asserting the fault request in response to the fault signal having a first asserted signal level and maintaining assertion of the fault request until a fault acknowledgement is received from a fault collection and control circuit.

Fault interface architecture in safety-relevant systems

In an integrated circuit, a first always on (AON) domain generates an isolation signal to enter standby mode. A switchable power domain propagates the isolation signal. A voltage level detector outputs an indicator which indicates whether a voltage of the switchable power supply is above or below a voltage threshold. An isolation wrapper circuit includes a pass-through latch selectively enabled based on the output of the voltage level detector. The pass-through latch receives the propagated isolation signal and provides a value of the propagated isolation signal at its output while enabled, but maintains a latched value at its output, regardless of changes in value of the propagated isolation signal, while disabled. The wrapper circuit also includes an isolation circuit which receives signals from circuitry within the switchable power domain and selectively isolates the received signals from a second AON power domain based on the output of the pass-through latch.

System on a chip (SoC) having a low power mode of operation

A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.

System and method for facilitating built-in self-test of system-on-chips

An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. The integrated circuit includes a wakeup detector including a plurality of inputs. Each input of the plurality of inputs is coupled to an external terminal circuit. The wakeup detector generates an output signal indicative of an external terminal of the plurality of external terminal circuits being placed at a wakeup voltage. The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode.

Low power mode testing in an integrated circuit

A switched fabric hierarchy (e.g., a PCIe hierarchy) may utilize hardware, firmware, and/or software for filtering duplicative or otherwise undesirable correctable error messages from reaching a root complex. An operating system of the root complex may detect a persistent stream or storm of correctable errors from a particular endpoint and activate filtering of correctable errors from that endpoint. A filtering device may receive filtering commands and parameters from the operating system, implement the filtering, and monitor further correctable errors from the offending device. While an offending device is being filtered, correctable error messages from the offending device may be masked from the operating system, while correctable error messages from other devices in the switched fabric hierarchy may be transmitted. At such time as the filtering device may detect that conditions for ending filtering of a device are met, the filtering device may cease filtering of the offending device and return monitoring responsibilities to the operating system.

Correctable error filtering for input/output subsystem

An address range expander associated with a processor and a physical memory device determines that address transformation has been enabled with respect to an address indicated on the processor's address bus. The expander generates, using one or more address expansion parameter registers, a transformed address corresponding to the untransformed address within an address range of the physical memory device, and transmits the transformed address to a controller of the physical memory device.

Address space expander for a processor

A firmware controller of a node of a distributed system determines a self-regulation threshold for at least one metric associated with traffic transmitted via an interconnect. The threshold is set to a value lower than the maximum permitted by the interconnect protocol. The controller transmits a request to an application-layer traffic endpoint to limit traffic based on the threshold. A hardware congestion management unit collects measurements on traffic metrics, including at least one metric other than the one for which the threshold is defined. Based on measurements obtained from the hardware congestion management unit, the controller modifies the self-regulation threshold and notifies the application-layer endpoint.

Congestion management in distributed systems using autonomous self-regulation

A system that includes a PCIe hierarchy may utilize a ring controller for message handling. Nodes acting as the root complex or as endpoint devices may include such ring controllers, portions of which may be implemented by dedicated circuitry on each node. The ring controllers may receive posted transactions representing messages, may return flow control credits for those transactions, may classify each message as to its type, and may write information about each message to a respective ring buffer storing information about messages of that type. A processor (or processing logic/circuitry) on the node may subsequently retrieve messages from the ring buffers and process them. The sizes and locations of the ring buffers in memory may be configurable by software (e.g., by writing to registers within the ring controllers). The message types may include correctable and non-correctable error messages, and non-error messages (including, but not limited to, vendor-defined messages).

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Round Rock, TX, United States of America

Joseph Rollin Wright