Sun Microsystems, Inc.

Joseph Raymond Siegel

Kenneth Alan House

Spencer Montgomery Gold

David J Greenhill

Claude R Gauthier

Pradeep R Trivedi

Emrys J Williams

Gin S Yee

Junji Sugisawa

Kamran Zarrineh

Steven R Boyle

Aiteen Zhang

Chen Li Lin

Ban-Pak Wong

Larry Kan

Joel Grinberg

A semiconductor device includes at least one component which is vulnerable to damage during scan testing for a particular input data configuration, and supports a safe mode in which this particular input data configuration is disabled. The semiconductor device also includes a port for receiving an input scan vector for scan testing, and an authorization unit connected to said port. The authorization unit maintains the device in safe mode if an input scan vector does not satisfy at least one predetermined criterion. In one particular implementation, the authorization unit generates a digital signature for the input scan vector, which is then compared to a signature portion included within the input scan vector itself. Scan testing is enabled providing that this comparison finds a match.

Semiconductor device and method and apparatus for testing such a device

A system and method is provided for scan control and observation of a logical circuit that does not halt the operation of the system clock. Thus, all dynamic circuits within the system continue to evaluate and precharge normally. Moreover, the traditional method of placing a multiplexer before the data input of a clocked storage element to perform scan control and observation is no longer required. Consequently, the system and method provide a more efficient manner in which to perform scan control and observation of a logical circuit.

Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip flops

A system and method are provided for sensing a physical stimulus of an integrated circuit. The system and method operate with one or more active thermal sensors embedded in the die of an integrated circuit to provide highly accurate die temperature measurements. The system and method are able to monitor and control the die temperature of the integrated circuit to avoid an integrated circuit malfunction due to an undesirable temperature condition.

Method and system for monitoring and profiling an integrated circuit die temperature

A dynamic sequential device is provided that is adapted for scan control and observation. The dynamic sequential device may be scanned in-circuit as part of a scan chain in a VLSI device or it may be scanned as a discrete device. The dynamic sequential device maintains performance with respect to speed while allowing control and observation of its internal machine states.

Scanable R-S glitch latch for dynamic circuits

A system and method for implementing an assertion check in an ATPG scan cell is provided. The assertion check includes an error signal generator within a scan cell that generates an error signal when there is a violation of necessary conditions for testing the integrated circuit using APTG. According to the illustrative embodiment, the scan cell comprises a set-reset flip-flop paired with a latch. The flip-flop is used as a master storage element and the latch is used as a slave storage element to form a scan path. The master flip-flop and the slave latch are connected to form a shift register for shifting test data through the circuit under test. A system clock drives the standard operational mode of the storage elements and a shift clock drives the test mode. An enable clock is used to activate the system clock and switch the scan cell between the standard operational mode and the test mode. The assertion check ensures that the enable clock and the shift clock are not both high at the same time by generating an error signal at the output of the flip-flop when both clocks are simultaneously high. The assertion check is implemented by adding a logic gate or a set of logic gates to the scan cell and connecting the output of the logic gate to the set and reset pins of the flip-flop, such that the flip-flop generates an error signal when both clocks are high.

Implementation of an assertion check in ATPG models

A dual edge-triggered flip-flop that may be programmably reset independent of a clock signal is provided. Using an externally generated reset value, the dual edge-triggered flip-flop may be asynchronously programmed to reset to either a logical high or a logical low. Further, a dual edge-triggered flip-flop that may be set to multiple triggering modes is provided. Using an externally generated enable signal, the dual edge-triggered flip-flop may be set to function as a single edge-triggered or a dual edge-triggered device. Thus, the dual edge-triggered flip-flop may be used multiple types of computing environments.

Dual edge-triggered flip-flop design with asynchronous programmable reset

Methods and systems for automatic generation of an at-speed binary counter are described. The binary counter includes a slow counter that increments when a fast counter overflows to keep up with a fast clock. A framework to automatically generate a Hardware Description Language (HDL) for an at-speed binary counter is also described.

System and method for automatic generation of an at-speed counter

The present invention provides logic to write data to a multi-ported memory array. The memory array is comprised of a plurality of memory banks and a common write word line shared by the memory banks. The memory array includes a plurality of write buffers, wherein each write buffer is associated with one of the memory banks. The memory array further comprises a selector module for selecting a write buffer to write data into its associated memory bank. The memory array further includes a writing module within the write buffer for writing data into the selected memory bank by way of a signal to the memory bank.

Memory array with common word line

A scannable latch for use within a circuit path of a series of one or more dynamic circuits is provided. The scannable latch provides both latch functionality during normal operation and scan test functionality during scan mode operation. Particularly, the scannable latch has a dynamic input stage and a shadow latch, where the dynamic input stage's primary function occurs during normal operations and where the shadow latch's primary function occurs during scan operations. The scannable latch also has an output gate operatively connected to the dynamic input stage and shadow latch.

Scannable latch for a dynamic circuit

A system and method for automatically selecting decoupling capacitors for an electronic device. The system determines a localized drive strength for each component in the electronic device. Based on a summation of drive strengths for components in a given area of the electronic device, the system determines whether a decoupling capacitor is necessary to provide local power bus stability.

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Shrewsbury, MA, United States of America

Joseph Raymond Siegel