Bell Telephone Laboratories

Joseph Raymond Ligenza

Dawon Kahng

Martin P Lepselter

Ernest Edward La Bate

An SI.sub.1 I.sub.2 M (semiconductor-insulator.sub.1 -insulator.sub.2 -metal) memory structure, containing an impurity such as tungsten concentrated in a region including the interface ('I.sub.1 I.sub.2 ') region between the I.sub.1 and I.sub.2 region, is fabricated by depositing an oxide of the impurity, such as tungsten trioxide, on the then exposed, I.sub.1 layer prior to fabricating the I.sub.2 layer. The oxide of the impurity, such as tungsten trioxide, can be advantageously deposited by means of reactive evaporation.

Method for fabricating multilayer insulator-semiconductor memory

Charge conditions are modified in a wafer including a silicon dioxide layer on a silicon substrate by introducing a distribution of tantalum into the silicon dioxide layer. The distribution of tantalum can be adapted to store negative charge, to getter sodium or to produce nonannealable fast surface states. A distribution of tantalum at the silicon-silicon dioxide interface produces nonannealable fast surface states. A distribution of tantalum in the silicon dioxide subjected to electrical and temperature stress can store negative charge and getter sodium. An n-channel insulated gate field effect transistor utilizes a silicon dioxide gate insulator which includes centrally located therein a region which is rich in treated tantalum.

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Califon, NJ, United States of America

Joseph Raymond Ligenza