Itt Corporation

Transwitch Corporation

Alcatel USA

Joseph R Yudichak

Herbert J Toegel

Daniel C Upp

William T Cochran

Jeffrey A Townsend

Shao H Liu

John F Gilsdorf

Pulse width controlled adaptive equalizers are provided for telecommunication signals which are routed over coaxial cables. The adaptive equalizers operate on the premise that a coaxial cable degrades a telecommunications signal by widening the pulse of the signal and decreasing the amplitude. The longer the cable is, the wider the pulse gets. Thus, by detecting the width of the pulse against a desired width, and feeding back the difference to a variable filter which can correct the pulse width, a pulse width controlled adaptive equalizer can be provided. The preferred pulse width controlled adaptive equalizer includes: a variable filter block for filtering input signals to provide frequency dependent gain based on the amplitude of a control signal; a comparator block for comparing the filtered bipolar signal against a reference value based on the peak amplitude of the signal to provide a pulsed output; a pulse width detector which senses the pulse width of the pulsed output and outputs a signal indicative of the pulse width; and a feedback filter which filters the signal indicative of the pulse width and provides a control signal to the variable filter in order to control the frequency dependent gain of the filter.

Receive side pulse width controlled adaptive equalizer

The transversal filter has a plurality of variable delay lines each having multiple voltage controlled delay stages in series, with one of the variable delay lines having a clock input, and the other variable delay lines having data signal inputs. A phase comparator is coupled to the output of two non-adjacent stages of the variable delay lines having the clock input. A feedback circuit is coupled to the comparator and provides voltage signals to the voltage controlled delay stages of all of the variable dealy lines, such that adjacent stages in a particular delay line are delayed in time equal fractions of a clock cycle from each other, and so that all delay lines are running on the same clock. A voltage weighting circuit is provided for shaping the voltage outputs of the data signal variable delay lines and the weighting circuit is coupled to the delay line stages by switches which are activated when a data signal is propagated through a delay line stage. Where positive pulse, zero pulse, and negative pulse inputs are provided to the transversal filter along with a clock signal, and where the delay lines of the transversal filter have four or more active stages, a substantially raised cosine B3ZS encoded waveform which can be transmitted over a coaxial cable of up to forty hundred fifty feet in length without requiring line build-out can be provided from an incoming B3ZS encoded DS3 signal.

Waveshaping transversal filter and method utilizing the same for data

A switch controller for a dynamic switch responds to command from a using system to provide control signals to the dynamic switch which causes the switch to establish and breakdown paths between sources and destinations in the using system. The controller includes a plurality of command registers which are temporarily assigned to a command source for receiving command signals, decoding said signals and providing control signals to the switch for establishing or breaking down a switch path. The controller may if desired provide an echo to a selected destination so that proper execution of commands may be ascertained. After the commands are completed the control register is released for reassignment to another command source while an established switch path remains intact. Thus, commands may be received from any source for controlling the switch.

Switch controller

A CAM/RAM/CAM memory array is used to provide dynamic space and time switching between a plurality of sources and destinations. The memory array includes a source CAM portion, a destination CAM portion and a data RAM portion with each row forming a word. In order to establish a path, a source address is stored in the source CAM portion of a word and a destination address is stored in the destination CAM portion of the same word. When data is to be switched, the data source address is presented to the source CAM on a TDM address bus to address a word having the same source address. The data is then written into the RAM of the addressed word from a data bus, if an address comparison is found. The address of the destination is time division multiplexed to the destination CAM via a destination address bus. If the address of the data destination on the address bus matches a stored address, the data RAM associated with the address is enabled and read to the data bus for delivery to the data destination. Means are further provided to dynamically assign and unassign addresses to and from words in the memory array to thereby dynamically establish switch paths.

Apparatus and method for providing dynamically assigned switch paths

A redundant clock combiner device includes a clock selecting latch that recovers a clock signal even if both externally supplied clocks fail. The clock selection occurs, and an output clock provided, even if the non-prioritized clock signal is restored before the prioritized clock signal.

Redundant clock combiner

An apparatus for establishing a plurality of communication paths includes a plurality of ports each having different data rates associated therewith and a means for establishing simultaneous paths among the plurality of ports according to instruction signals from terminals interfaced with the ports and carried on the same path as the information to be switched.

Growing community of inventors

Madison, CT, United States of America

Joseph R Yudichak