Synopsys, Inc.

Joseph R Walston

Mathew V Philip

Stylianos Diamantidis

Piyush Verma

Amzie Adams

A method includes generating a plurality of intermediate designs for a chip by executing a first sub-step based on a first plurality of inputs, adding at least one intermediate design of the plurality of intermediate designs to a second plurality of inputs, generating a plurality of final designs by executing a second sub-step of the step of the design flow based on the second plurality of inputs, and selecting using a machine learning model a final design from the plurality of final designs. The first sub-step is a sub-step of a step of a design flow and the first plurality of inputs corresponds to input parameters associated with the first sub-step.

Dividing a chip design flow into sub-steps using machine learning

A set of parameter values may be generated by a machine learning (ML) model, where the set of parameter values may be used by a black-box function to generate a set of outputs based on a set of inputs. It may be determined whether the set of parameter values is expected to cause the set of outputs generated by the black-box function to violate one or more desired goals. If so, a first response may be provided to the ML model that discourages the ML model from generating sets of parameter values that are similar to the set of parameter values. Otherwise, the set of parameter values may be provided to the black-box function, a second response may be determined based on the set of outputs generated by the black-box function, and the second response may be provided to the ML model.

In-situ function parameter search space filtering for machine learning in electronic design automation

A method and apparatus for aggregating multiple component metrics into a single reward function output value (AOV) is disclosed. The method comprises determining at least one component metric value to be used to determine the AOV. In addition, the method comprises determining at least one component metric target value to strive to achieve. Furthermore, the method comprises determining at least one baseline value to use when determining the AOV. Still further, the method comprises determining unacceptable values for particular component metrics. The method also comprises combining at least one component metric value into a single AOV and optimizing component input values to achieve the best AOV.

Aggregating multiple component metrics into a single reward function

A request may be received to use a software on a first project. A first set of values may be extracted for a set of features of the first project. A classifier may be used to classify the first project based on the first set of values. It may be determined whether to grant the request to use the software on the first project based on an output of the classifier.

Fail-safe software access licensing control on a per project basis without a priori knowledge of project details

A method includes receiving a crash signature and a crash configuration. The crash signature is generated in response to a software crash in a software application caused by the crash configuration. The method also includes applying a first machine learning model to determine a reference of a plurality of references that is closest to the crash signature and the crash configuration. The reference includes a reference crash signature and a reference configuration. The reference crash signature and the reference configuration are generated by a proxy crash to the software crash. The proxy crash was generated prior to the software crash by executing a modified test case against the software application.

Machine learning technique to diagnose software crashes

A method for optimizing a circuit design includes computing clock latency estimates for a set of sequential circuit elements, modifying the clock latency estimates based on relative optimizability of (1) a set of input data paths that are electrically coupled to one or more inputs of the sequential circuit element and (2) a set of output data paths that are electrically coupled to one or more outputs of the sequential circuit element, and optimizing the circuit design based on the modified clock latencies.

Growing community of inventors

Durham, NC, United States of America

Joseph R Walston