Advanced Micro Devices Corporation

Ati Technologies Ulc

Advanced Micro Device, Inc.

Joseph R Siegel

Bryan Black

Michael Zhouying Su

Gamal Refai-Ahmed

Anwar Kashem

Dales Morrison Kent

Dwight K Elvey

Seth Prejean

Michael S Alfano

Michael Bienek

Julius Din

Kevin M Gillespie

Harry R Fair

Ronnie Brandon

Various interposers and methods of manufacturing related thereto are disclosed. In one aspect, an apparatus is provided that includes an interposer that has a first side and a second side opposite the first side. The first side has a first reticle field and a second reticle field larger than the first reticle field. Plural conductor pads are positioned on the first side in the first reticle field. Plural dummy conductor pads are positioned on the first side in the second reticle field and outside the first reticle field.

Interposer with beyond reticle field conductor pads

A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip.

Semiconductor chip with thermal interface tape

A fault tolerant scannable glitch latch for use with scan chains that enable reset, debug and repairability of machines and parts is described. A scan shift enable signal controls a switch such that a stuck-at zero fault on a data input line is prevented from driving voltage to a state node or pulling the state node high during a scan chain operation. Propagation of the stuck-at zero fault is therefore eliminated. The scan shift enable signal also controls a switch that enables a parallel path to ground for the scan data and state node which would otherwise have been driven high due to the stuck-at zero fault.

Fault tolerant scannable glitch latch

A method to test and package dies so as to increase overall yield is provided. The method includes performing a wafer test on a first die and mounting the first die on a package substrate to form a partial package, if the wafer test of the first die is successful. The method further includes performing a system test on the partial package including the first die and stacking a second die on the first die if the system test on the partial package and the first die is successful.

Die stacking, testing and packaging for yield

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Brookline, MA, United States of America

Joseph R Siegel