Tektronix, Inc.

Joseph R Peter

Raymond Hayes

Steven K Sullivan

Kei-Wean Calvin Yang

Bruce W Blair

Luis J Navarro

John E Taggart

A CMOS-compatible peak detection circuit includes a differential amplifier stage (10), an active peak holding circuit (12), and a passive peak holding circuit (14). The differential amplifier stage (10) produces an amplifier output signal that is responsive to the difference between an input signal being monitored and feedback from the active peak holding circuit (12). Both the active peak holding circuit (12) and the passive peak holding circuit (14) store a charge representing a voltage level that is indicative of the peak amplitude of the amplifier output signal during a time interval, the time interval occurring while a disable signal is inactive. The active peak holding circuit (12) provides the maximum value signal as feedback to the differential amplifier stage (10). The passive peak holding circuit (14) provides a max signal output corresponding to the maximum value to a voltage follower stage (16) that makes it available as an output when a readback enable signal goes active. The active and passive peak holding circuits (12,14) are disconnected from the output of the differential amplifier stage (10) when a disable signal is active. A reset signal discharges capacitor storage (C1,C2) in the peak holding circuits (12,14) when it goes active. The readback enable and reset signals only go active during the time that the disable signal is active. To conserve power, a bias generation circuit (18) provides bias signals to the differential amplifier stage (10) enabling it to conduct only when the disable signal is inactive.

Peak detection circuit

A serial-parallel-serial, charged-coupled device includes an array of horizontal rows and columns of closely spaced charge storage cells. Each storage cell is formed by an electrode covering an insulation layer above a semiconductor substrate. The semiconductor substrate of each storage cell includes a channel region for conducting carriers laterally through the storage cell. The channel region of each storage cell included both in a first row of the array and in any column of the array has a tilted potential gradient providing an electric field facilitating charge carrier drift within the channel region in two lateral directions, toward a neighboring storage cell of the first row and also toward a neighboring storage cell of its column.

Tilted channel, serial-parallel-serial, charge-coupled device

A two phase shift register comprises four serial registers each having an input section, a transfer section, and a lead-in section disposed between the input section and the transfer section. The input sections provide respective sequences of charge samples, the four sequences being offset in phase relative to each other by 90.degree. within the cycle of a clock signal. At least one of the serial registers comprises a first lead-in gate pair and a second lead-in gate pair over the lead-in section, the second lead-in gate pair being between the first lead-in gate pair and the transfer section. The first lead-in gate pair and the second lead-in gate pair are each driven at the frequency of the clock signal, the drive signal applied to the second lead-in gate pair being retarded in phase relative to that applied to the first lead-in gate pair by 90.degree. within the cycle of the clock signal.

Charge-coupled device shift register

A charge coupled device (CCD) analog shift register in a two-channel serial-parallel-serial (SPS) structure operating in a fast-in/slow-out (FISO) mode for high speed signal acquisition and temporary storage of a plurality of samples. The two CCD arrays are clocked simultaneously, and the input analog signal is demultiplexed to the two arrays. Additional transfer electrodes are provided at the input of one of the arrays, and the other array is provided with a sampling clock which is 180.degree. out of phase with the sampling clock of the first array; two consecutive samples of the input signal are taken during each transfer clock cycle. All signal samples are clocked through the arrays simultaneously and appear at the output at the same time.

High speed data acquisition utilizing multiple charge transfer delay

High speed data acquisition utilizing multiplex charge transfer devices

A signal-envelope display system for a digital oscilloscope includes a memory for storing minimum and maximum signal values in adjacent storage locations, an address counter for sequentially addressing the memory, and a control circuit for selectively inverting the least significant bit of the address count signal. The values retrieved from the memory are converted to analog values and a low-pass filter connects the analog values to provide a signal envelope display.

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Beaverton, OR, United States of America

Joseph R Peter