International Business Machines Corporation

Joseph R Mathis

Richard G Fogg, Jr

Carl Zeitler, Jr

William G Kulpa

Ballard J Blevins

James O Nicholson

Richard R Oehler

John W McCullough

Gerald L Rouse

A data processing system including a processor that issues communications commands on a first communications channel and a peripheral device that is connected to the first communications channel and to a second communications channel that operates asynchronously relative to the first communications channel. The peripheral device performs communications operations specified from the commands from the processor and further responds to communications over the second communications channel. The peripheral device includes a controller that provides a status word to the processor in response to the command issued to the peripheral device. The status word indicates the status condition of the peripheral device at the time when the peripheral device initiates the operation specified by the issued command.

Input/output initiate command mechanism

A DMA controller has an attached, dedicated memory. Data objects are stored on the heap and connected by pointers. Each data object contains DMA block transfer control parameters. A single block transfer made up of several separate transfers, with each separate transfer defined by one data object. The single block transfer is defined by linking several data objects into a list. The DMA controller consecutively performs the transfers in a linked list without requiring control by a system central processor.

System for DMA block data transfer based on linked control blocks

A system for transferring data between a pair of data processing units having system buses includes a plurality of memories in each of the data processing units; each memory having a random access portion and an associated sequential access portion; means for transferring data between each of the random access portions of each of the memories and its associated sequential access portion; and means connecting the sequential access portions of each of the memories in one of the data processing units to the sequential access portions of the other of said data processing units to permit data flow therebetween; the data flow between the sequential access portions of said memories occurring asynchronously of the remainder of the system so that the data processing units can utilize their system buses during such data flow.

Multi-processor communications channel utilizing random

In a network communications system, data is transferred from a first node to a second node. When requested, the second node can transmit a data direction turnaround message to the first node, followed by transferring data to the first node. Data transfer in both directions is made during a single communications link within the network. The turnaround message can function as an acknowledgement of successful transfer to the data transferred from the first node to the second node.

Transfer direction turnaround in network data communications

In a communications system, a sending system and a receiving system have multiple data buffers. In response to an inquiry from the sending system, the receiving system transmits information which indicates the size and number of data buffers available in the receiving system. The sending system then begins transmitting data frames, which are placed into the buffers of the receiving system. When the receiving system removes all of the data from a buffer, therefore freeing it to accept additional data, it sends a signal to the sending system indicating this fact. The sending system counts such signals, and ensures that the number of transmitted data frames does not exceed the number of frames which have been removed from the receiver's buffers by more than the number of buffers which the receiver has.

System and method for data communications

An improvement in a bus converter that provides a bus to bus address translation function permitting access from an I/O device connected on the I/O bus to a system bus and system memory, where the bus converter includes a circuit connected to the I/O bus to partition I/O addresses received from the I/O bus into a lower order field and a high order field and connected to a circuit to receive DMA ID's from the I/O bus to combine this DMA ID with the high order field to form a first combined address. The first combined address is input to a memory which provides corresponding control field and prefix field data. An address formatter is further included that is connected to receive the control field and prefix field data from the memory and further connected to receive the low order address field. The address formatter forms a second combined address from the prefix field, control field and lower order address field. This second combined address is then provided to a system bus to permit access to the system bus.

Bus to bus converter using a RAM for multiple address mapping

A composite shift register timer for controlling a sequence of events occurring over a demand-response interface. The composite shift register comprises a primary shift register and a secondary shift register. The primary shift register is divided into successive portions which are selectively coupled together in successive pairs upon timely receipt of respective response signals. A first binary '1' is inserted into the first portion at the start of a predetermined sequence of events. The first '1' is clocked through to the end of the first portion where it initiates a demand and is stored pending the receipt of a corresponding response. A second binary '1' is clocked through the secondary shift register beginning with the initiation of each demand. The clocking of the second '1' continues until the receipt of a timely response to the initiated demand whereupon the secondary shift register is reset. The timely response also is applied to the coupling means between the first and second portions of the primary shift register to permit the stored first '1' to propagate into and be clocked through the second portion. If no timely response is received, the second '1' propagates to the end of the secondary shift register to produce an 'error' signal. The error signal deactivates each coupling means between the portions of the first shift register to prevent the first binary '1' from propagating any farther, thus terminating the sequence of events.

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Georgetown, TX, United States of America

Joseph R Mathis