Bae Systems Information and Electronic Systems Integration Inc.

Lockheed Martin Corporation

Lockhead Martin Corp.

Joseph R Marshall, Jr

Alan F Dennis

Daniel L Stanley

Richard J Ferguson

Charles A Dennis

Steven G Santee

Dale G Langston

Richard Berger

Dale A Rickard

John C Rodgers

Jason F Ross

John T Matta

George A Sawyer

An MCM-HIC device flexibly adds enhanced features to a VLSI 'core' IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one 'chiplet' that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or 'mixed' chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.

Multi-chip hybrid system-in-package for providing interoperability and other enhanced features to high complexity integrated circuits

A method for providing a power estimation for an electronic system is disclosed. Initially, a system architecture of an electronic system design is initially developed, and the system architecture of the electronic system design is then converted to a power flow architecture of the electronic system design. For each power domain within the power flow architecture of the electronic system design, a power domain type is designated. Subsequently, power information are added to the power flow architecture of the electronic system. Finally, a power roll-up calculation is performed on the power flow architecture of the electronic system design in order to yield a final system power value for the electronic system design.

Method and apparatus for providing power estimations for electronic system designs

A universal support device for supporting a reconfigurable electronics device is disclosed. The universal support device includes an application specific integrated circuit (ASIC) module coupled to multiple non-volatile memory devices. The ASIC module is capable of interfacing with an external reconfigurable electronics device via a set of load/read-back interface lines and sense mitigation lines. The load/read-back interface lines are capable of being programmed to provide a parallel or a serial load and/or store protocols. The sense mitigation line can sense conditions that indicate a single-event functional interrupt or a radiation-induced event occurred within the reconfigurable electronics device.

Universal non-volatile support device for supporting reconfigurable processing systems

Chalcogenide technology is used for radiation hardening for spaceborne systems and more particularly in C-RAM form for processors, field programmable gate arrays, startup RAMs, shadow storage and single-chip systems to protect these units.

Use of radiation-hardened chalcogenide technology for spaceborne reconfigurable digital processing systems

A reconfigurable digital processing system for space includes the utilization of field programmable gate arrays utilizing a hardware centric approach to reconfigure software processors in a space vehicle through the reprogramming of multiple FPGAs such that one obtains a power/performance characteristic for signal processing tasks that cannot be achieved simply through the use of off-the-shelf processors. In one embodiment, for damaged or otherwise inoperable signal processors located on a spacecraft, the remaining processors which are undamaged can be reconfigured through changing the machine language and binary to the field programmable gate arrays to change the core processor while at the same time maintaining undamaged components so that the signal processing functions can be restored utilizing a RAM-based FPGA as a signal processor. In one embodiment, multiple FPGAs are connected together by a data bus and are also provided with data pipes which interconnect selected FPGAs together to provide the necessary processing function. Flexibility in reconfiguration includes the utilizing of a timing and synchronization block as well as a common configuration block which when coupled to an interconnect block permits reconfiguration of a customizable application core, depending on the particular signal processing function desired. The result is that damaged or inoperable signal processing components can be repaired in space without having to physically attend to the hardware by transmitting to the spacecraft commands which reconfigure the particular FPGAs thus to alter their signal processing function. Also mission changes can be accomplished by reprogramming the FPGAs.

Reconfigurable digital processing system for space

A computer device includes an interface board, a plurality of peripheral component interface (PCI) busses on the interface board, and a plurality of device card connectors carried by the interface board. The plurality of device card connectors include at least one first device card connector coupled to first and second PCI busses synchronous with one another, and at least one second device card connector coupled to the second PCI bus and to a third PCI bus asynchronous with the second PCI bus. The PCI busses are thus connected so that the PCI busses may be added in groups according to the number of device card connectors supported by the interface board, and not by the loading constraints of the PCI busses themselves. By defining both synchronous and asynchronous device card connectors, device cards requiring either synchronous or asynchronous communications may be utilized by the computer device. Each device card includes an interface bridge for connecting to a respective asynchronous or synchronous device card connector.

Computer device having multiple linked parallel busses and associated method

A lockstep processor system adds error detection, isolation, and recovery logic to one or more lockstep processor system functions; namely, control outputs, processor inputs, I/O busses, memory address busses, and memory data busses.

Growing community of inventors

Manassas, VA, United States of America

Joseph R Marshall, Jr