International Business Machines Corporation

Joseph R Greco

Qizhi Liu

Aaron Vallett

Robert F Vatter

Arne Watson Ballantine

Douglas Duane Coolbaugh

Peter John Geiss

Jeffrey D Gilbert

Richard Steven Kontra

Glenn Robert Miller

Emily Lanning

James Albert Slinkman

Randy Lee Wolf

Richard A Phelps

Timothy Charles Krywanczyk

Steven Ross Codding

Jennifer C Robbins

Kevin Munger

William Savaria

Nicholas Mone, Jr

Eric J Caprarola

Robert C Churchill

Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

Vertical p-type, n-type, p-type (PNP) junction integrated circuit (IC) structure

Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure

Various particular embodiments include an integrated circuit (IC) structure including: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

Method to build vertical PNP in a BiCMOS technology with improved speed

Various particular embodiments include a method of amorphizing a portion of silicon underneath the N+ base section of a PNP transistor structure. After amorphizing, the method can include selectively etching that implant-amorphized silicon to trim the collector-base area and collector-base junction. The selective etching is enhanced because the unimplanted silicon region etches at a distinct rate than the implant-amorphized silicon, allowing for control over the trimming of the collector-base junction.

Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure, and methods of forming

An electromagnetic electron reflector, an ion implanter having an electromagnetic reflector and a method of implantation using the ion implanter. The electromagnetic electron reflector includes a frame; permanent magnets within the frame; a center aperture within the frame and electrically isolated by first gaps from the frame and the permanent magnets and fixed in position by dielectric feed throughs, first cup shields integrally formed on the top and bottom edges of the center aperture, the dielectric feed throughs nested within the first cup shields; second cup shields integrally formed on inside surfaces of the top and bottom of the frame, the second cup shields nested within respective first cup shields; entrance and exit apertures attached to the frame and an electrical conductor passing through at least one of the dielectric feed throughs and electrically contacting the center aperture.

Electromagnetic electron reflector

A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.

Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic suppressing region

Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region

A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method includes forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.

Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structure

A method of recycling monitor wafers. The method includes: (a) providing a semiconductor wafer which includes a dopant layer extending from a top surface of the wafer into the wafer a distance less than a thickness of the wafer, the dopant layer containing dopant species; after (a), (b) attaching an adhesive tape to a bottom surface of the wafer; after (b), (c) removing the dopant layer; and after (c), (d) removing the adhesive tape.

Method for recycling of ion implantation monitor wafers

A wafer processing method. The method includes providing a semiconductor wafer. The semiconductor wafer includes (i) a semiconductor layer and (ii) a dopant layer on top of the semiconductor layer. The dopant layer comprises dopants. The method further includes removing the dopant layer from the semiconductor wafer. No chemical etching is performed on the dopant layer before said removing the dopant layer is performed.

Recycling of ion implantation monitor wafers

A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.

Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures

A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Growing community of inventors

South Burlington, VT, United States of America

Joseph R Greco